參數(shù)資料
型號(hào): M37207MF-XXXSP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64
封裝: 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁(yè)數(shù): 60/124頁(yè)
文件大小: 1993K
代理商: M37207MF-XXXSP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)
37
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00DC16) to “0.” The first 7-bit ad-
dress data transmitted from the master is compared with the high-
order 7-bit slave address stored in the I2C address register (ad-
dress 00DA16). At the time of this comparison, address compari-
son of the RBW bit of the I2C address register (address 00DA16)
is not made. For the data transmission format when the 7-bit ad-
dressing format is selected, refer to Figure 34, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00DC16) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I2C address
register (address 00DA16). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I2C address regis-
__
ter (address 00DA16) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
__
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I2C status register (address 00DB16) is set to “1.” After
the second-byte address data is stored into the I2C data shift register
(address 00D916), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I2C address register (address 00DA16) to “1” by software. This
__
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I2C address register (address 00DA16). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 34, (3) and (4).
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00DA16) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00DD16).
Set “1016” in the I2C status register (address 00DB16) and hold
the SCL at the HIGH.
Set a communication enable status by setting “4816” in the I2C
control register (address 00DC16).
Set the address data of the destination of transmission in the high-
order 7 bits of the I2C data shift register (address 00D916) and set
“0” in the least significant bit.
Set “F016” in the I2C status register (address 00DB16) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I2C data shift register (address 00D916).
At this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
.
Set “D016” in the I2C status register (address 00DB16). After this,
if ACK is not returned or transmission ends, a STOP condition will
be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00DA16) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “2516
in the I2C clock control register (address 00DD16).
Set “1016” in the I2C status register (address 00DB16) and hold
the SCL at the HIGH.
Set a communication enable status by setting “4816” in the I2C
control register (address 00DC16).
When a START condition is received, an address comparison is
made.
When all transmitted addresses are “0” (general call) :
AD0 of the I2C status register (address 00DB16) is set to “1” and
an interrupt request signal occurs.
When the transmitted addresses match the address set in
:
AAS of the I2C status register (address 00DB16) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above :
AD0 and AAS of the I2C status register (address 00DB16) are
set to “0” and no interrupt request signal occurs.
Set dummy data in the I2C data shift register (address 00D916).
When receiving control data of more than 1 byte, repeat step
.
When a STOP condition is detected, the communication ends.
相關(guān)PDF資料
PDF描述
M37207M8-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64
M37207MF-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64
M37210M3-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PQFP64
M37210E4-XXXSP 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37210E4FP 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PQFP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M3720-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND
M3720-9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND
M37210E4 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M37210E4-801FP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
M37210E4FP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER