![](http://datasheet.mmic.net.cn/30000/M37161MA-XXXFP_datasheet_2359598/M37161MA-XXXFP_20.png)
Rev.1.00
2003.11.25
page 20 of 128
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
Fig. 8.3.4 Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
Name
After reset
Functions
RW
Interrupt Control Register 1
0
Timer 1 interrupt
enable bit (TM1E)
0 : Interrupt disabled
1 : Interrupt enabled
1
Timer 2 interrupt
enable bit (TM2E)
2
Timer 3 interrupt
enable bit (TM3E)
3
4
OSD interrupt enable bit
(OSDE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
R —
7
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
Timer 4 interrupt
enable bit (TM4E)
0 : Interrupt disabled
1 : Interrupt enabled
5
VSYNC interrupt enable
bit (VSCE)
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
6
INT3 external interrupt
enable bit (IN3E)
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
Fig. 8.3.5 Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address 00FF16]
B
Name
Functions
After reset RW
Interrupt Control Register 2
0
INT1 external interrupt
enable bit (IN1E)
0 : Interrupt disabled
1 : Interrupt enabled
1
2
Serial I/O interrupt
enable bit (SIE)
3
4
INT2 external interrupt
enable bit (IN2E)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0R W
RW
0R W
f(XIN)/4096 interrupt
enable bit (CKE)
0 : Interrupt disabled
1 : Interrupt enabled
5
Multi-master I2C-BUS
interface interrupt enable
bit (IICE)
0 : Interrupt disabled
1 : Interrupt enabled
6
Timer 5 6 interrupt
enable bit (TM56E)
0 : Interrupt disabled
1 : Interrupt enabled
7
Timer 5 6 interrupt
switch bit (TM56C)
0 : Timer 5
1 : Timer 6
0R W
Fix this bit to “0.”
0