參數(shù)資料
型號： M3455AGC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52
封裝： 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52
文件頁數(shù)： 88/148頁
文件大?。?/td> 1807K
代理商： M3455AGC-XXXFP
Rev.1.02
Nov 26, 2008
Page 44 of 146
REJ03B0224-0102
455A Group
LCD FUNCTION
The 455A Group has an LCD (Liquid Crystal Display)
controller/ driver. When data are set in LCD RAM and timer LC,
LCD control registers (L1, L2, L3, C1, C2, C3), and timer
control registers (W3, W4), the LCD controller/driver
automatically reads the display data and controls the LCD
display by setting duty and bias.
4 common signal output pins and 32 segment signal output pins
can be used to drive the LCD. By using these pins, up to 128
pixels (when internal power, 1/4 duty and 1/3 bias are selected)
can be controlled to display. When using the external input, set
necessary pins with the LCD control register 2 and apply the
proper voltage to the pins .
The LCD power input pins (VLC3–VLC1) are also used as pins
SEG0–SEG2. When SEG0 is selected, the internal power (VDD)
is used for the LCD power.
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select
the proper display method for the LCD panel being used.
1/2 duty, 1/2 bias
1/3 duty, 1/3 bias
1/4 duty, 1/3 bias
Table 18
Duty and maximum number of displayed
pixels
Note. Leave unused COM pins open.
Fig 43. LCD controller/driver
Duty
Maximum number of displayed
pixels
Used COM pins
1/2
64 pixels
COM0, COM1 (Note)
1/3
96 pixels
COM0–COM2 (Note)
1/4
128 pixels
COM0–COM3
Common
driver
Bias control
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Selector
LCD RAM
Register A
Selector
L12
L20
L23
VDD
L23
L22
L21
L13
L11
L10
Decoder
LCD ON/OFF
control
1/2, 1/3, 1/4
counter
LCD clock
(from timer LC)
CO
M
3
CO
M
2
CO
M
1
CO
M
0
SEG
0
/V
LC
3
SEG
1
/V
LC
2
SEG
2
/V
LC
1
SEG
3
....
P0
0
/S
E
G
16
C1
0
to
C
1
3
L2
3
L2
2
L2
1
C2
0
to
C
2
3
L3
0
to
L
3
C3
0
to
C
3
P0
3
/S
E
G
19
P1
0
/S
E
G
20
P1
3
/S
E
G
23
P2
0
/S
E
G
24
P2
3
/S
E
G
27
P3
0
/S
E
G
28
P3
3
/S
E
G
31
SEG
15
r
....
r
to
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