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Rev.1.02
Nov 26, 2008
REJ03B0224-0102
455A Group
Recommended operating conditions
Note 1. At 1/2 bias: VLC1 = VLC2 = (1/2)VLC3
At 1/3 bias: VLC1 = (1/3)VLC3, VLC2 = (2/3)VLC3
Note 2. The average output current is the average value during 100ms.
Table 31 Recommended operating conditions 1 (Ta = –20
°C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Unit
Min.
Typ.
Max.
VDD
Supply voltage
(with a ceramic resonator)
f(STCK)
≤ 6MHz
4
5.5
V
f(STCK)
≤ 4.4MHz
2.7
5.5
f(STCK)
≤ 2.2MHz
2
5.5
f(STCK)
≤ 1.1MHz
1.8
5.5
VDD
Supply voltage
(when an external clock is
used)
f(STCK)
≤ 4.8MHz
4
5.5
V
f(STCK)
≤ 3.2MHz
2.7
5.5
f(STCK)
≤ 1.6MHz
2
5.5
f(STCK)
≤ 0.8MHz
1.8
5.5
VDD
Supply voltage
(when quartz-crystal oscillation
is used)
f(STCK)
≤ 50 kHz
1.8
5.5
V
VDD
Supply voltage
(Low-speed/High-speed on-
chip oscillator is used)
1.8
5.5
V
VRAM
RAM back-up voltage
(at RAM back-up)
1.6
5.5
V
VSS
Supply voltage
0V
VLC3
1.8
VDD
V
VIH
“H” level input voltage
P0, P1, P2, P3, D0–D7
0.8VDD
VDD
V
XIN, XCIN
0.7VDD
VDD
RESET
0.85VDD
VDD
INT
0.85VDD
VDD
CNTR
0.8VDD
VDD
VIL
“L” level input voltage
P0, P1, P2, P3, D0–D7
00.2VDD
V
XIN, XCIN
00.3VDD
RESET
00.3VDD
INT
00.15VDD
CNTR
0
0.15VDD
IOH(peak)
“H” level peak output current
P0, P1, P2, P3, D0–D5
VDD = 5V
20
mA
VDD = 3V
10
C/CNTR
VDD = 5V
30
VDD = 3V
15
IOH(avg)
“H” level average output current
P0, P1, P2, P3, D0–D5
VDD = 5V
10
mA
VDD = 3V
5
C/CNTR
VDD = 5V
20
VDD = 3V
10
IOL(peak)
“L” level peak output current
P0, P1, P2, P3, D0–D7, C/CNTR
VDD = 5V
24
mA
VDD = 3V
12
RESET
VDD = 5V
10
VDD = 3V
4
IOL(avg)
“L” level average output current
P0, P1, P2, P3, D0–D7, C/CNTR
VDD = 5V
15
mA
VDD = 3V
7
RESET
VDD = 5V
5
VDD = 3V
2
ΣIOH(avg)
“H” level total average current
P0, C/CNTR
40
mA
P1, P2, P3, D0
D5
40
ΣIOL(avg)
“L” level total average current
P0, C/CNTR
40
mA
P1, P2, P3, D0
D7, RESET
40