參數(shù)資料
型號: M34554EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 64/138頁
文件大?。?/td> 1082K
代理商: M34554EDFP
Rev.3.00
Aug 06, 2004
page 31 of 136
REJ03B0043-0300Z
4554 Group
TIMERS
The 4554 Group has the following timers.
Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a set-
ting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload reg-
ister, and count continues (auto-reload function).
Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency divid-
ing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
Fig. 24 Auto-reload function
The 4554 Group timer consists of the following circuits.
Prescaler : 8-bit programmable timer
Timer 1 : 8-bit programmable timer
Timer 2 : 8-bit programmable timer
Timer 3 : 8-bit programmable timer
Timer 4 : 8-bit programmable timer
Timer 5 : 16-bit fixed dividing frequency timer
Timer LC : 4-bit programmable timer
Watchdog timer : 16-bit fixed dividing frequency timer
(Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively)
Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the
timer control registers PA, W1 to W6. The watchdog timer is a free
counter which is not controlled with the control register.
Each function is described below.
FF16
n
0016
n : Counter initial value
Count starts
Reload
1st underflow
2nd underflow
n+1 count
Time
An interrupt occurs or
a skip instruction is executed.
Timer interrupt
request flag
T
h
e
c
o
n
te
n
ts
o
f
c
o
u
n
te
r
“1”
“0”
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