參數(shù)資料
型號(hào): M34506M2-XXXFP
元件分類(lèi): 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO20
封裝: 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁(yè)數(shù): 4/114頁(yè)
文件大?。?/td> 836K
代理商: M34506M2-XXXFP
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
4
4-12
EIT
32180 Group User’s Manual (Rev.1.0)
4.8 Exception Processing
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in
hardwarepreprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.
Also, save the accumulator and FPSR register as necessary.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time,
the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure
4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruc-
tion exception suggests that the system has some fatal fault already existing in it. In such a case, therefore,
do not return from the reserved instruction exception handler to the program that was being executed when
the exception occurred.
4.8.2 Address Exception (AE)
[OccurrenceConditions]
Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions. The following lists the combination of instructions and accessed addresses that may cause
address exceptions to occur.
Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’
Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’
When an address exception occurs, memory access by the instruction that generated the exception is not
performed. If an external interrupt is requested at the same time an address exception is detected, it is the
address exception that is accepted.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM
SM
BIE
IE
BC
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM
Unchanged
IE
0
C
0
(3) Saving the PC
The PC value of the instruction that generated the address exception is set in the BPC register. For ex-
ample, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC
register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set
in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that
generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on
a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT handler
has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned
to the PC.)
相關(guān)PDF資料
PDF描述
M34507E4FP 4-BIT, OTPROM, MICROCONTROLLER, PDSO24
M34507M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34507M4-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34507M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34509G4FP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34506M4 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34506M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
M34507E4FP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34507M2-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
M34507M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER