參數(shù)資料
型號(hào): M34283G2-XXXGP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝: 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件頁(yè)數(shù): 45/64頁(yè)
文件大小: 484K
代理商: M34283G2-XXXGP
Rev.1.01
Mar 20, 2006
page 5 of 62
REJ03B0109-0101
4283 Group
CONNECTIONS OF UNUSED PINS
(Note when connecting to VSS and VDD)
Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Control
bits
1 bit
Output:
2 bits
Input:
3 bits
4 bits
1 bit
Control
instructions
SD
RD
CLD
SD
RD
CLD
SZD
OEA
IAE
OGA
IAG
SCAR
RCAR
Control
registers
PU1
PU0
Output structure
P-channel open-drain
CMOS
Input/
Output
(4)
I/O
(4)
I/O
(2)
Input
(1)
I/O
(4)
Output
(1)
Remark
Pull-down function and
key-on wakeup function
(programmable)
Pull-down function and
key-on wakeup function
(programmable)
Pull-down function and
key-on wakeup function
(programmable)
Pin
D0–D3
D4–D7
E0
E1
E2
G0–G3
CARR
Port
Port D
Port E
Port G
Port CARR
DEFINITION OF CLOCK AND CYCLE
System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the CCK
instruction.
CCK instruction
When not using
When using
Instruction clock
f(XIN)/32
f(XIN)/4
System clock
f(XIN)/8
f(XIN)
Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
Machine cycle
The machine cycle is the cycle required to execute the
instruction.
Pin
D0–D3
D4–D7
E0, E1
E2
G0–G3
CARR
Connection
Open.
Connect to VDD.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open.
Connect to VSS.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open.
Usage condition
Pull-down transistor OFF.
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