參數(shù)資料
型號(hào)： M34283G2-XXXGP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件頁(yè)數(shù)： 11/64頁(yè)
文件大?。?/td> 484K
代理商： M34283G2-XXXGP
Rev.1.01
Mar 20, 2006
page 19 of 62
REJ03B0109-0101
4283 Group
Fig. 21 Internal state at reset
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage at operating and to reset the microcomputer if
the supply voltage drops below the specified value (Typ. 1.50 V)
or less.
The voltage drop detection circuit is stopped and power
dissipation is reduced in the RAM back-up mode with the
initialized CPU stopped.
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
A battery exchange of an application product is explained as
an example.
The supply voltage falls below to the recommended operating
voltage while CPU keeps active. Then, an unexpected
oscillation-stop, which does not happen by POF instruction
occurs before the supply voltage falls below to the detection
voltage. In this time, even if the supply voltage re-goes up to
the recommended operating voltage, since reset does not
occur, MCU may not operate correctly.
Please confirm the oscillator you use and the frequency of
system clock, and test the operation of your system sufficiently.
Fig. 22 Voltage drop detection circuit operation waveform
Program counter (PC) ..............................................................
Address 0 in page 0 is set to program counter.
Power down flag (P) .................................................................
Timer 1 underflow flag (T1F) ...................................................
Timer 2 underflow flag (T2F) ...................................................
Timer control register V1 ..........................................................
Timer control register V2 ..........................................................
Port CARR output flag (CAR) ..................................................
Pull-down control register PU0 ................................................
Pull-down control register PU1 ................................................
Logic operation selection register LO ......................................
Most significant ROM code reference enable flag (URS)
Carry flag (CY) .........................................................................
Register A .................................................................................
Register B .................................................................................
Register X .................................................................................
Register Y .................................................................................
Stack pointer (SP) ....................................................................
VDD
Internal reset signal
Reset voltage
TYP 1.5V
(Note)
Note: The voltage drop detection circuit does not have
the hysteresis characteristics in the detected voltage.
Microcomputer starts operation
after f(XIN) is counted to 16384 times.
000
00
0
000
0
000
0
000
0
00
0
111
1
111
1
11
Fig. 23 VDD and VDET
VDD
Recommended operatng
condition min.value
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
Oscillation is stopped
incorrectly.
VDET
VDD
Recommended
operatng condition
min.value
VDET
→ Normal operation
Reset
“” represents undefined.
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