![](http://datasheet.mmic.net.cn/30000/M32196F8UFP_datasheet_2359476/M32196F8UFP_37.png)
1
1-17
OVERVIEW
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
Port
Function 1
Function 2
DRI function
NBD function
Function
Type
State during
reset
State upon
exiting reset
1
P221/CRX0/HREQ#
P221
CRX0(Note 1) HREQ#(Note 1)
-
Input
P221
Input
Hi-Z
During single-chip and
external extension modes
P225
Input
Hi-Z
During processor mode
A12
Output
Hi-Z
Undefined
3
VSS
-
VSS
-
VSS
-
4
XIN
-
XIN
-
Input
XIN
Input
-
5
XOUT
-
XOUT
-
Output
XOUT
Output
XOUT
6
VCC-BUS
-
VCC-BUS
-
VCC-BUS
-
During single-chip and
external extension modes
P224
Input
Hi-Z
During processor mode
A11
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P30
Input
Hi-Z
During processor mode
A15
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P31
Input
Hi-Z
During processor mode
A16
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P32
Input
Hi-Z
During processor mode
A17
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P33
Input
Hi-Z
During processor mode
A18
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P34
Input
Hi-Z
During processor mode
A19
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P35
Input
Hi-Z
During processor mode
A20
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P36
Input
Hi-Z
During processor mode
A21
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P37
Input
Hi-Z
During processor mode
A22
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P20
Input
Hi-Z
During processor mode
A23
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P21
Input
Hi-Z
During processor mode
A24
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P22
Input
Hi-Z
During processor mode
A25
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P23
Input
Hi-Z
During processor mode
A26
Output
Hi-Z
Undefined
20
VCC-BUS
-
VCC-BUS
-
VCC-BUS
-
21
VSS
-
VSS
-
VSS
-
During single-chip and
external extension modes
P24
Input
Hi-Z
During processor mode
A27
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P25
Input
Hi-Z
During processor mode
A28
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P26
Input
Hi-Z
During processor mode
A29
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P27
Input
Hi-Z
During processor mode
A30
Output
Hi-Z
Undefined
During single-chip and
external extension modes
P00
Input
Hi-Z
During processor mode
DB0
Input/output
Hi-Z
VCC-BUS
TO21(Note 1)
7
P224/A11/CS2#
P224
A11
CS2#(Note 1)
-
TIN30
TIN31
TIN32
TIN33
CS3#(Note 1)
TIN4
TIN5
TIN6
Condition
Function
Pin
No.
Pin state when reset
Symbol
Type
Power
supply
-
Input/
output
DD16
Input/
output
-
Input/
output
2
P225/A12/CS3#
8
P30/A15/TIN4/DD16
P30
A15
P225
A12
9
P31/A16/TIN5/DD17
P31
A16
DD19
Input/
output
10
P32/A17/TIN6/DD18
P32
A17
TIN7
DD17
Input/
output
DD18
Input/
output
DD20
Input/
output
11
P33/A18/TIN7/DD19
12
P34/A19/TIN30/DD20
P34
A19
P33
A18
13
P35/A20/TIN31/DD21
P35
A20
DD23
Input/
output
14
P36/A21/TIN32/DD22
P36
A21
DD21
Input/
output
DD22
Input/
output
DD24
Input/
output
15
P37/A22/TIN33/DD23
16
P20/A23/DD24
P20
A23
P37
A22
17
P21/A24/DD25
P21
A24
DD27
Input/
output
18
P22/A25/DD26
P22
A25
DD25
Input/
output
DD26
Input/
output
DD28
Input/
output
19
P23/A26/DD27
22
P24/A27/DD28
P24
A27
P23
A26
23
P25/A28/DD29
P25
A28
Input/
output
24
P26/A29/DD30
P26
A29
25
P27/A30/DD31
DD31
-
P00
DB0
P27
A30
26
P00/DB0/TO21/DD0
VCC-BUS
DD0(Note 1)
Input/
output
DD29
Input/
output
DD30
Input/
output
The pins directed for input go to a high-impedance state (Hi-Z) when reset. The term “when reset” means that
input on RESET# pin is held “L” (the device remains reset), and that the RESET# pin is released back “H” (the
device comes out of reset).
Table 1.4.1 Pin Assignments of the M32192F8xFP, M32195F4xFP, and M32196F8xFP (1/4)
Note 1: The pins outputted at two places.
1.4 Pin Assignments