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參數資料
| 型號： | M32176F2TFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數： | 20/36頁 |
| 文件大?。?/td> | 342K |
| 代理商： | M32176F2TFP |
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27
32176 Group
Mitsubishi Microcomputers
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Under Development
Jan. 30, 2003
Rev.1.4
16-channel A-D Converters
The microcomputer contains 16-channel A-D0 converters
with 10-bit resolution. In addition to single conversion on
each channel, continuous A-D conversion on a combined
group of N (N = 1-16) channels is possible. The A-D con-
verted value can be read out in either 10-bit or 8-bit.
In addition to ordinary A-D conversion, the converters sup-
port comparator mode in which the set value and A-D con-
verted value are compared to determine which is larger or
smaller than the other.
Moreover, there is also Sample & hold function, input volt-
age is sampled, when A-D conversion is started, and the A-
D conversion of the sampling voltage is carried out.
Since there is no invalid domain near [which becomes a
problem by the external operational amplifier etc.] VCCE/
VSS, conversion by the full range is possible in this sample
& hold circuit.
When A-D conversion is finished, the converters can gener-
ate a DMA transfer request, as well as an interrupt.
Table 13. Outline of the A-D Converters
Item
Content
Analog input
16-channel
A-D conversion method
Successive approximation method
Resolution
10-bit (Conversion results can be read out in either 10 or 8-bit)
Absolute accuracy (Note 1)
During low speed mode : Normal mode: + 2 LSB, double speed mode: + 2 LSB
(conditions: Ta = 25°C,
During high speed mode : Normal mode: + 3 LSB, double speed mode: + 3 LSB
AVCC0, 1 = VREF0, 1 = 5.12V)
Note: The performance is the same during sample & hold function.
Conversion mode
A-D conversion mode, comparator mode
Operation mode
Single mode, single-shot scan mode, continuous scan mode
Conversion start trigger
Software start
Started by setting A-D conversion start bit to 1
Hardware start
MJT input event bus 2, MJT input event bus 3, MJT output event bus 3, and MJT (TIN23S)
Conversion Speed
During single mode
Low-speed mode
Normal
299 BCLK
14.95
s
f(BCLK): Internal peripheral
(Unavailable for Sample & Hold
Double speed
173 BCLK
8.65
s
clock operating frequency
Available for Normal
High-speed mode
Normal
131 BCLK
6.55
s
(Note 2)
Sample & Hold)
Double speed
89 BCLK
4.45
s
During single mode
Low-speed mode
Normal
191 BCLK
9.55
s
(Available for High-speed
Double speed
101 BCLK
5.05
s
Sample & Hold)
High-speed mode
Normal
95 BCLK
4.75
s
Double speed
53 BCLK
2.65
s
During comparator mode
Low-speed mode
Normal
47 BCLK
2.35
s
Double speed
29 BCLK
1.45
s
High-speed mode
Normal
23 BCLK
1.15
s
Double speed
17 BCLK
0.85
s
Sample & hold function
Validity/invalidity selectable
A-D disconnection detection
Influences of the analog input voltage wrapping around from the preceding channel are suppressed when
assist function
operating scan mode.
Interrupt request generation
When A-D conversion is finished, when comparate operation is finished
When single-shot scan is finished, or when one cycle of continuous scan is finished
DMA transfer
When A-D conversion is finished, when comparate operation is finished
request generation
When single-shot scan is finished, or when one cycle of continuous scan is finished
Note 1: The rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when
themicrocomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board.
Note 2: Conversion time at the time of f(BCLK) = 20 MHz operation (1 BCLK = 50 ns)
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