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參數(shù)資料
| 型號： | M32176F2TFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 342K |
| 代理商： | M32176F2TFP |
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20
32176 Group
Mitsubishi Microcomputers
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Under Development
Jan. 30, 2003
Rev.1.4
Built-in 10-Channel DMAC
The microcomputer contains 10 channels of DMAC, allow-
ing for data transfer between internal peripheral I/Os, be-
tween internal RAM and internal peripheral I/O, and be-
tween internal RAMs.
DMA transfer requests can be issued from the user-created
software, as well as can be triggered by a signal generated by
the internal peripheral I/O (A-D converter, timer, or serial I/O).
The microcomputer also supports cascaded connection be-
tween DMA channels (starting DMA transfer on a channel at
end of transfer on another channel). This makes advanced
transfer processing possible without causing any additional
CPU load.
Table 11. Outline of the DMAC
Item
Content
Number of channels
10 channels
Transfer request
Software trigger
Request from internal peripheral I/O: A-D converter, timer, or serial I/O (reception completed,
transmit buffer empty)
Cascaded connection between DMA channels possible (Note 1)
Maximum number of times transferred
256 times
Transferable address space
64K bytes (address space from H’0080 0000 to H’0080 FFFF)
Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO,
and between internal RAMs are supported
Transfer data size
16-bit or 8-bit
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-
address transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination of transfer:
Address fixed
Address increment
32-channel ring buffer
Channel priority
DMA 0 > DMA 1 > DMA 2 > DMA 3 > DMA 4 > DMA 5 > DMA 6 > DMA 7 > DMA 8 > DMA 9
(Fixed priority)
Maximum transfer rate
13.3M bytes per second (when internal peripheral clock = 20 MHz)
Interrupt request
Group interrupt request can be generated when each transfer count register underflows
Transfer area
64K bytes from H ’0080 0000 to H ’0080 FFFF (Transfer is possible in the entire internal RAM/
SFR area)
Note 1: The following DMA channels can be cascaded.
DMA transfer on channel 1 started at end of one DMA transfer on DMA 0
DMA transfer on channel 2 started at end of one DMA transfer on DMA 1
DMA transfer on channel 0 started at end of one DMA transfer on DMA 2
DMA transfer on channel 4 started at end of one DMA transfer on DMA 3
DMA transfer on channel 6 started at end of one DMA transfer on DMA 5
DMA transfer on channel 7 started at end of one DMA transfer on DMA 6
DMA transfer on channel 5 started at end of one DMA transfer on DMA 7
DMA transfer on channel 9 started at end of one DMA transfer on DMA 8
DMA transfer on channel 5 started at end of all DMA transfers on DMA 0 (underflow of transfer count register)
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