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參數(shù)資料
| 型號(hào)： | M32000D4BFP-80 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 32 Bits Microcomputer(32位 單片機(jī)) |
| 中文描述： | 32位單片微機(jī)（32位單片機(jī)） |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
23
When writing word-size data aligned on the 32-bit boundary, the
M32000D4BFP-80 carries out a burst-transfer by outputting the
BURST signal. When burst-writing 32-bit data, the MSB-side 16-bit
write bus cycle is driven first, followed by the LSB-side 16-bit write
bus cycle. The BURST signal is synchronized with the CLKIN falling
edge of the first bus access cycle, and "L" level is output. It returns to
"H" level in synchronization with the CLKIN falling edge of the last
bus access cycle. Addresses A8 to A30 are output for each cycle.
When an "L" level is input to HREQ, the M32000D4BFP-80 switches
to the hold state and outputs an "L" level to HACK. While the
M32000D4BFP-80 is in the hold state, bus related pins go to a high
impedance state, and data transfer is carried out on the system bus.
To return to normal operation mode from the hold state, the HREQ
signal should be changed to an "H" level.
Fig. 21 1-word (32-bit) burst write timing (1-0 wait)
Fig. 22 Bus arbitration timing
"Hi-Z"
"Hi-Z"
"Hi-Z"
(see note 2)
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
Notes 1:
Before switching to the hold state, an idle cycle of 1 CLKIN clock period is always
inserted.
After returning from the hold state, an idle cycle of 1 to 5 CLKIN clock periods is
3:
when the CS signal is input.
(see note 2)
(see note 3)
write
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
idle
hold shift
hold
return
idle
HACK
SID, ST
(see note 1)
(see note 1)
BS
BURST
idle
CLKIN
BS
A8 - A30
SID,ST
BCH, BCL
BURST
D0 - D15
DC
R/W
burst write (1 word)
idle
"Hi-Z"
"Hi-Z"
Note:
"Hi-Z" means high-impedance, and indicates sampling timing.
Wait cycles can be inserted even when burst transferring by
setting DC = "H".
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