
9
2
3
f
o
5
0
2
,
2
0
.
g
u
A
0
.
1
.
v
e
R
0
1
0
-
7
8
1
0
B
9
0
J
E
R
Page 136
16. Serial I/O
p
u
o
r
G
0
8
/
C
6
1
M
Figure 16.12 Serial I/O-related registers (8)
Address
When reset
U2SMR3
033516
000XXXXX2
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
U3SMR3
032516
000000002
U4SMR3
02F516
000000002
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
SSE
SS port function enable bit 0: SS function disable
1: SS function enable
0: Without fault error
1: With fault error
CKPH
DINC
NODC
ERR
Clock phase set bit
Serial input port set bit
Clock output select bit
0: Select TxDi and RxDi
(master mode) (Note 5)
1: Select STxDi and SRxDi
(slave mode) (Note 6)
0: CLKi is CMOS output
1: CLKi is N-channel open drain
output
Fault error flag
(Note 3)
(Note 4)
0: Without clock delay
1: With clock delay
000:Without delay
001:1 to 2 cycles of 1/f(XIN)
010:2 to 3 cycles of 1/f(XIN)
011:3 to 4 cycles of 1/f(XIN)
100:4 to 5 cycles of 1/f(XIN)
101:5 to 6 cycles of 1/f(XIN)
110:6 to 7 cycles of 1/f(XIN)
111:7 to 8 cycles of 1/f(XIN)
SDA2(TxD2) digital
delay time set bit
(Note 1,2)
DL0
DL1
DL2
UART2 special mode register 3
Note 1: These bits are used for SDA2(TxD2) output digital delay when using UART2 for IIC interface.
Otherwise, must set to "000".
Note 2: When external clock is selected, delay is increased approx. 100ns.
UARTi special mode register 3 (i=3,4)
000 :Without delay
001 :1 to 2 cycles of 1/f(XIN)
010 :2 to 3 cycles of 1/f(XIN)
011 :3 to 4 cycles of 1/f(XIN)
100 :4 to 5 cycles of 1/f(XIN)
101 :5 to 6 cycles of 1/f(XIN)
110 :6 to 7 cycles of 1/f(XIN)
111 :7 to 8 cycles of 1/f(XIN)
SDAi(TxD2) digital
delay time set bit
(Note 1,2)
DL0
DL1
DL2
Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface.
Otherwise, must set to "000".
Note 2: When external clock is selected, delay is increased approx. 100ns.
Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control
register 0) to "1".
Note 4: Nothing but "0" may be written.
Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the
RxDi function select register A for input/output port and the port direction register to "0".
Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and
SRxDi function select register A for input/output port and the port direction register to "0".
b7 b6 b5
Nothing is assigned. These bits can neither be set nor reset. When read,
their contents are indeterminate.