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Contents for change
Revision
date
Version
C - 2
Revision History
p
u
o
r
G
0
8
/
C
6
1
M
'98.10.19
Page 165 figure 1.34.3
operation clock --> BCLK
Page 169
they function as output regardless of the contents of the direction registers. When pins
are to be used as the outputs for the D/A converter, do not set the direction registers to
output mode.
-->
set the corresponding function select registers A, B and C. When pins are to be used
as the outputs for the D/A converter, set the function select register of each pin to I/O
port, and set the direction registers to input mode.
Table 1.35.1 lists each port and peripheral function.
All page
M30800MC-XXXFP --> M16C/80 (100-pin version) group
Page 2 Figure 1
changed, GP package is added
Page 3 Figure 3
Note 1 and Note 2 is added
Page 5 Figure 4, Table 2
New type no. is added
Page 6 Figure 5
GP is added
Page 10 Line 2
18 registers --> 28 registers
Page 11 (7) Set USP and ISP to an even number so that execution efficiency is increased.
--> added
Page 17 Figure 11 (54) UART4 special mode register 3 --> added
Page 18 Figure 12
UART3 special mode register 3 --> added
UART2 special mode register 3 --> added
Function select register B3 --> added
Page 20 Figure 14
UART4 special mode register 3 --> added
UART3 special mode register 3 --> added
UART2 special mode register 3 --> added
Page 21 Figure 15 Function select register B3 --> added
Page 24 Figure 23 PM1 Note 4 -->added
Page 31 Figure 26
Page 45 Table 14, Page 46 Table 15
Note --> added
Page 50 Figure 32-4
Changed
Page 51 Line 6
port function select register 3 --> function select register A3
Page 52 Line 17
FFFFE416 to FFFFE716 are all --> FFFFE716 is
Page 53 Table 17 BRK instruction
If the vector is --> If the contents of FFFFE716 is
Page 53 Table 18
Instruction fetch and DBC --> delated
Page 58 Figure 36 IPL --> RLVL
Page 61 Figure 38 004D16 --> 009316
Page 67 Figure 44-1Note 3 and 6 --> added
Page 68 Figure 45 memory --> memory (forward direction)
Page 70 Figure 46-2DMAi memory address reload register Note:
vector register (SVP) --> save PC register (SVP)
Page 84 Figure 56 Note 4 addresses 034216 and 034316 --> address 034316
Page 93 Table 30
Count source: TBj overflow --> added
Page 96 Figure 69
Three-phase PWM control register 0 Note 4:both bit 0 and 1 --> bit 1
REV.B
'98.3.2
REV.C