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Clock asynchronous serial I/O (UART) mode
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Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
147
Item
Specification
Transfer data format
Transfer data 8-bit UART mode (bit 2 to 0 of addresses 0338
16
, 0328
16
, 02F8
16
= “101
2
”)
One stop bit (bit 4 of addresses 0338
16
, 0328
16
, 02F8
16
= “0”)
With the direct format chosen
Set parity to “even” (bit 5 and 6 of addresses 0338
16
, 0328
16
, 02F8
16
= “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 033D
16
= “0”).
Set transfer format to LSB (bit 7 of address 033C
16
= “0”).
With the inverse format chosen
Set parity to “odd” (bit 5 and 6 of addresses 0338
16
, 0328
16
, 02F8
16
= “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 033D
16
= “1”)
Set transfer format to MSB (bit 7 of address 033C
16
= “1”)
With the internal clock chosen (bit 3 of
addresses 0338
16
, 0328
16
, 02F8
16
= “0”)
: fi / 16 (n + 1)
(Note 1) : fi=f
1
, f
8
, f
32
With an external clock chosen (bit 3 of
addresses 0338
16
, 0328
16
, 02F8
16
= “1”)
: f
EXT
/ 16 (n+1)
(Note 1) (Note 2)
Disable the CTS and RTS function (bit 4 of address 033C
16
, 032C
16
, 02FC
16
= “1”)
The sleep mode select function is not available for UART2
Set transmission interrupt factor to “transmission completed” (bit 4 of address 033D
16
,
032D
16
, 02FD
16
= “1”)
Set N-channel open drain output to TxD and RxD pins in UART3 and 4 (bit 5 of
address 032C
16
, 02FC
16
= “1”)
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 033D
16
, 032D
16
, 02FD
16
) = “1”
- Transmit buffer empty flag (bit 1 of address 033D
16
, 032D
16
, 02FD
16
) = “0”
To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 033D
16
, 032D
16
, 02FD
16
) = “1”
- Detection of a start bit
When transmitting
When data transmission from the UART2 to UART4 transfer register is completed (bit
4 of address 033D
16
, 032D
16
, 02FD
16
= “1”)
When receiving
When data transfer from the UART2 to UART4 receive register to the UART2 to
UART4 receive buffer register is completed
Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
Framing error (see the specifications of clock-asynchronous serial I/O)
Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxD
i
pin by use of the parity
error signal output function (bit 7 of address 033D
16
, 032D
16
, 02FD
16
= “1”) when a
parity error is detected
- On the transmission side, a parity error is detected by the level of input to the RxD
i
pin when a transmission interrupt occurs
The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 00
16
to FF
16
that is set to the UARTi bit rate generator.
Note 2: f
EXT
is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
UARTi receive interrupt request bit is not set to “1”.
Transfer clock
Transmission / reception control
Other settings
Transmission start condition
Reception start condition
Error detection
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some
extra settings in UART2 to UART4 clock-asynchronous serial I/O mode allows the user to effect this function.
Table 1.19.1 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Interrupt request
generation timing
that the
Table 1.19.1. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)