參數(shù)資料
型號： M306S0FA-XXXGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 15.36 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, LQFP-64
文件頁數(shù)： 26/207頁
文件大?。?/td> 1628K
代理商： M306S0FA-XXXGP
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Rev.5.00
Apr 24, 2009
page 121 of 200
REJ03B0014-0500
M16C/6S Group
Table 1.16.4. I2C Mode Functions
Special Mode
Function
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
Clock Synchronous Serial I/O
Mode (SMD2 to SMD0 = 001b,
IICM = 0)
Factor of Interrupt Number
15, 17 and 19 (1, 6)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Factor of Interrupt Number
16, 18 and 20 (1, 6)
Start condition detection or stop condition detection
(See Table 1.16.5 STSPSEL Bit Functions)
UARTi Transmission
Output Delay
Functions of P6_3, P6_7
and P7_0 Pins
Noise Filter Width
Read RXDi and SCLi Pin
Levels
Factor of Interrupt Number
6, 7 and 10 (1, 5, 7)
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
Initial Value of TXDi and
SDAi Outputs
UARTi transmission
Transmission started or
completed (selected by UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TXDi output
RXDi input
CLKi input or output selected
15ns
Possible when the
corresponding port direction bit
= 0
CKPOL = 0 (H)
CKPOL = 1 (L)
Delayed
SDAi input/output
SCLi input/output
(Cannot be used in I2C mode)
Initial and End Values of
SCLi
H
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C mode (2)
Timing for Transferring
Data From the UART
Reception Shift Register to
the UiRB Register
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 1
(Clock delay)
CKPH = 1
(Clock delay)
UARTi transmission
Rising edge of
SCLi 9th bit
UARTi transmission
Falling edge of SCLi
next to the 9th bit
UARTi reception
Falling edge of SCLi 9th bit
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Rising edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
Falling and rising
edges of SCLi 9th
bit
Functions of P6_2, P6_6
and P7_1 Pins
Functions of P6_1, P6_5
and P7_2 Pins
i = 0 to 2
NOTES :
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to Changing the Interrupt Generate Factor.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled).
3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
4. First data transfer to UiRB register (Falling edge of SCLi 9th bit)
5. See Figure 1.16.4 STSPSEL Bit Functions.
6. See Figure 1.16.2 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision).
DMA1 Factor (6)
UARTi reception
Acknowledgment detection
(ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store Received Data
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
1st to 8th bits of the received
data are stored into bits 7 to 0
in the UiRB register
1st to 7th bits of the received data are
stored into bits 6 to 0 in the UiRB
register. 8th bit is stored into bit 8 in the
UiRB register.
L
Bits 6 to 0 in the UiRB
register (4) are read as
bits 7 to 1. Bit 8 in the
UiRB register is read as
bit 0.
Read Received Data
The UiRB register status is read
CKPH = 0
(No clock delay)
CKPH = 0
(No clock delay)
H
L
1st to 8th bits are stored
into bits 7 to 0 in the
UiRB register (3)
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