參數(shù)資料
型號(hào)： M30624FGPGP-U5
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 37/87頁(yè)
文件大小： 919K
代理商： M30624FGPGP-U5
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
o
4
0
2
,
1
0
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e
S
0
3
.
2
.
v
e
R
Z
0
3
2
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-
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0
B
3
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page 42
Table 5.27 Memory Expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Symbol
Standard
Measuring
Condition
Max.
Min.
Parameter
Unit
td(BCLK-AD)
Address Output Delay Time25ns
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)4
ns
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)4
ns
td(BCLK-ALE)
ALE Signal Output Delay Time15
ns
th(BCLK-ALE)
ALE Signal Output Hold Time
–4
ns
td(BCLK-RD)
RD Signal Output Delay Time25ns
th(BCLK-RD)
RD Signal Output Hold Time
0
ns
td(BCLK-WR)
WR Signal Output Delay Time25ns
th(BCLK-WR)
WR Signal Output Hold Time0
ns
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)40ns
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)(3)
4ns
th(WR-DB)
Data Output Hold Time (in relation to WR)(3)
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
ns
1. Calculated according to the BCLK frequency as follows:
f(BCLK)
(n–0.5) X 109
– 40
[ns]
td(BCLK-CS)
Chip Select Output Delay Time25ns
th(RD-AD)
Address Output Hold Time (in relation to RD)0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)(NOTE 2)ns
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1k
, hold time
of output “L” level is
t = – 30pF X 1k
X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.
DBi
R
C
(NOTE 1)
(NOTE 2)
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
n is “1” for 1-wait setting, “2” for 2-wait
setting and “3” for 3-wait setting.
When n=1, f(BCLK) is 12.5MHz or less.
– 10
NOTES:
HLDA Output Delay Time
40ns
td(BCLK-HLDA)
See Figure 5.2
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