![](http://datasheet.mmic.net.cn/30000/M30260M3A-XXXGP-U5_datasheet_2358673/M30260M3A-XXXGP-U5_315.png)
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19. Usage Precaution
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19.5.5 INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
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input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
3. When using the INT5 interrupt for exiting stop mode, set the P17DDR register to “FF16” (disable digital
debounce filter) before entering stop mode.
19.5.6 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewritten, due to the internal bus and the instruction queue buffer timing.