M30245 Group
Clock asynchronous serial I/O (UART) mode
Rev.2.00
Oct 16, 2006
page 137 of 264
REJ03B0005-0200
Clock asynchronous serial I/O (UART) mode
UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table
1.46 lists the specifications of the UART mode.
Table 1.46. Specifications of clock asynchronous serial I/O mode
Note 1: 'm' denotes the value 00 16 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the value of the UiRB register will be indeterminate. The IR bit of
the SiRIC register does not change.
Item
Specification
Transfer data format
Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Start bit: 1 bit
Parity bit: odd, even, or neither is selected
Stop bit: 1 bit or 2 bits as selected
Transfer clock
When internal clock is selected (bit 3 at address 03A816, 036816, 033816, 032816 = "0"): fi/
16(m+1) (Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at address 03A816, 036816, 033816, 032816 = "1"):
fEXT/16/(m+1) (Notes 1, 2)
Transmission/reception control
CTS function, RTS function, CTS/RTS function chosen to be invalid
Transmission start condition
To start transmission, the following requirements must be met:
-Transmit enable bit (bit 0 at addresses 03AD16, 036D16, 033D16, 032D16) = "1"
-Transmit buffer empty flag (bit 1 at address 03AD16, 036D16, 033D16, 032D16) = "0"
-When CTS function is selected CTS input level = "1"
Receive start condition
To start receive, the following conditions must be met:
-Receive enable bit (bit 2 at addresses 03AD16, 036D16, 033D16, 032D16) = "1"
-Start bit detection
Interrupt request
generation timing
When transmitting
-Transmit interrupt cause select bits (bit 4 at address 03AD16, 036D16, 033D16, 032D16) =
"0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi
transmit register is complete.
-Transmit interrupt cause select bits (bit 4 at address 03AD16, 036D16, 033D16, 032D16) =
"1": Interrupts requested when data transmission from UARTi transfer register is complete.
When receiving
-Interrupts requested when data transfer from UARTi receive register to UARTi receive
buffer register is complete.
Error detection
Overrun error (Note 3)
This error occurs if the serial I/O starts receiving the next data and receives the 7th bit
of the next data before reading the UiRB register.
Framing error
This error occurs when the number of stop bits set is not detected
Parity error
If parity is enabled this error occurs when the number of "1"s in parity and character bits
does not match the number of "1"s set
Error sum flag
This flag is set (=1) when any overrun, framing, and parity error occurs
Select function
Serial data logic switch
This function reverses the logic of transferred data. Start bit, parity bit and stop bit are not
reversed.
TxD, RxD I/O polarity switch
This function reverses the TxD port output and RxD port input. All I/O data levels are
reversed.