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M30245 Group
Usage Notes
Rev.2.00
Oct 16, 2006
page 251 of 264
REJ03B0005-0200
Pulse modulation mode
The Timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the
following procedures:
Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode.
Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to “0” after the above listed
changes have been made.
Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAiOUT
pin is outputting an “H” level in this instance, the output level goes to “L”, and the Timer Ai interrupt request bit goes to
“1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the Timer Ai interrupt
request bit does not becomes “1”.
A/D converter
Write to each bit (except bit 6) of AD control register 0, AD control register 1, and to bit 0 of AD control register 2
when A/D conversion is stopped (before a trigger occurs). When the VREF connection bit is changed from "0" to “1”,
wait 1 s or longer before starting A/D conversion.
When changing A/D operation mode, select the analog input pin again.
Using one-shot mode or single sweep mode:
Read the corresponding AD register after confirming A/D conversion is finished. (Check the A/D conversion interrupt
request bit.)
Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1:
Use the undivided main clock as the internal CPU clock.
When f(Xin) is faster than 10MHz, make the A/D frequency 10MHz or less by dividing.
Description
Serial I/O (UART Mode)
When the CLKi and CTSi pin level goes to “H” (Note 1), if the UiMR register is set to either of the
following settings, the UiERE bit of the UiC1 register is set to “1” (parity error signal output enabled).
When the PRYE bit of the UiMR register is set to “1” while the UiERE bit is “1” (parity error signal output
enabled), if a parity error occurs at receiving data, the TXDi pin outputs the “L” level. To prevent this, set
the UiERE bit after setting the UiMR register.
Set bits SMD2 through SMD0 to “0002” (serial I/O disabled) through “1012” (UART mode transfer data
8 bits long)
Set bits SMD2 through SMD0 to “0012” (clock synchronous serial I/O mode) through “1002” (UART
mode transfer data 7 bits long)
Set bits SMD2 through SMD0 to “0012” (clock synchronous serial I/O mode) through “1012” (UART
mode transfer data 8 bits long)
Set bits SMD2 through SMD0 to “0012” (clock synchronous serial I/O mode) transfer data 9 bits long)
Set bits SMD2 through SMD0 to “0102” (I2C mode) through “1012” (UART mode transfer data 8 bits
long)
Note 1: If the pins are not used as CLKi or CTSi, these conditions apply when the pin level goes to “H”.