參數(shù)資料
型號： M30240M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 72/125頁
文件大小： 753K
代理商： M30240M4-XXXFP
CONFIDENTIAL
52
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
Figure 37:
USB Interrupt Enable Register 2
The USB Frame Number Low Register, shown in Figure 38, contains the lower 8 bits of the 11-bit
frame number received from the host. The USB Frame Number High Register, shown in Figure 39
contains the upper 3 bits of the 11-bit frame number received from the host.
Figure 38:
USB Frame Number Low Register
Figure 39:
USB Frame Number High Register
The USB ISO Control Register, shown in Figure 40, contains two global bits, ISO_UPD and AUTO_FL
for endpoints 1-4 regarding the isochronous data transfer.
If ISO_UPD = “0”, a data packet in an endpoint’s IN FIFO is always ‘ready to transmit’ upon receiving
the next IN_TOKEN from the host (with matched address & endpoint number). If ISO_UPD = “1” and
the ISO bit of the corresponding endpoint’s IN CSR is set, then the internal ‘ready to transmit’ signal
to the transmit control logic is delayed until the next SOF. In this way, the data loaded in frame n is
transmitted out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1 to 4, and works with iso-
chronous pipes only.
If AUTO_FL = “1”, ISO_UPD = "1", and a particular IN endpoint’s ISO bit is set, then at the time the
USB FCU detects a SOF packet, if the corresponding IN endpoint’s IN_PKT_RDY = “1”, the USB FCU
automatically flushes the oldest packet from the IN FIFO. In this case, IN_PKT_RDY = “1” indicates
that two data packets are in the IN FIFO. Since, for ISO transfer, double buffering is a requirement,
MAXP must be set to less than or equal to 1/2 of the FIFO size.
INTEN8
USB Endpoint 4 IN Interrupt Enable Bit (bit 0)
INTEN9
USB Endpoint 4 OUT Interrupt Enable Bit (bit 1)
Bit 3:2
Reserved (Read/Write “0”)
INTEN12
USB Overrun/Underrun Interrupt Enable Bit (bit 4)
Bit 5
Reserved
Bit 6
Reserved
Bit 7
Reserved
0: Interrupt disabled
1: Interrupt enabled
MSB
7
LSB
0
Reserved
INTEN12
Reserved
INTEN9
INTEN8
Access: R/W
Reset:
3316
Address: 030516
Reserved
FN7:0
Lower 8 bits of the 11-bit frame number issued with a SOF token
MSB
7
LSB
0
FN7
FN6
FN5
FN4
FN3
FN1
FN0
Access: R
Reset:
0016
FN2
Address: 030616
FN10:8
Upper 3 bits of the 11-bit frame number issued with a SOF token
Bits 7:3
Reserved (Read “0”)
MSB
7
LSB
0
Reserved Reserved Reserved Reserved Reserved
FN9
FN8
Access: R
Reset:
0016
FN10
Address: 030716
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