參數(shù)資料
型號: M30240M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 13/125頁
文件大?。?/td> 753K
代理商: M30240M4-XXXFP
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
13
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Central Processing Unit (CPU)
Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”
when the interrupt is acknowledged.
Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this
flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software inter-
rupts 0 to 31 is executed.
Bits 8 to 11: Reserved area
Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor
interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is en-
abled.
Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the M16C software manual
for details.
Figure 6:
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
C
D
Z
S
B
O
I
U
IPL
b0
b15
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