參數(shù)資料
型號(hào)： M30102F3TFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 65/164頁
文件大?。?/td> 3302K
代理商： M30102F3TFP
REVISION HISTORY
M30100/M30102 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
156
Explanation of “(5) Pulse period measure mode” is partly revised.
Explanation of precaution is partly revised.
Figure 1.14.4 is partly revised.
Explanation of Timer Y is partly revised.
Explanation of “(2) Programmable waveform generation mode” is partly revised.
Figure 1.14.5 is partly revised.
Figure 1.14.6 is partly revised.
Note 1 and Note 2 are added to Timer Y, Z mode register in Figure 1.14.6.
Explanation of Timer Z is partly revised.
Figure 1.14.7 is partly revised.
Figure 1.14.9 is partly revised.
Explanation of “(2) Programmable waveform generation mode” is partly revised.
Explanation of “Timer C” is partly revised.
Figure 1.14.10 is partly revised.
Note 1 is added to Timer C control register 0 in Figure 1.14.10.
Figure 1.14.11 is partly revised.
Figure 1.14.12 is partly revised.
Table 1.14.1 and its Note are partly revised.
Figure 1.15.1 is partly revised.
Note is added to UARTi transmit/receive mode register in Figure 1.15.4 is partly revised.
UARTi transmit/receive control register 0 in Figure 1.15.4 is partly revised.
Note 1 and Note 2 of UARTi transmit/receive control register 0 in Figure 1.15.4 are deleted .
Note 1 is added to UARTi transmit/receive control register 1 in Figure 1.15.5.
UARTi transmit/receive control register 2 is added to Figure 1.15.5.
Table 1.15.2 is partly revised.
Figure 1.15.10 is partly revised.
Table 1.15.3 is partly revised.
Table 1.15.4 is partly revised.
Explanation of “A-D Converter” is partly revised.
Table 1.16.1 is partly revised.
Figure 1.16.1 is partly revised.
A-D control register 0 in Figure 1.16.2 is partly revised.
Figure 1.16.3 is partly revised.
“Input pin” and Note in Table 1.16.3 are revised.
Figure 1.16.5 is partly revised.
Explanation of “Extended analog input pins” is partly revised.
Explanation of “External operation amp connection mode” is partly revised.
Explanation of “D-A Converter” is partly revised.
Figure 1.17.1 is partly revised.
Figure 1.17.3 is partly revised.
Explanation of “Programmable I/O Ports” is partly revised.
Figure 1.18.2 is revised.
Figure 1.18.3 is revised.
Figure 1.18.4 is revised.
Figure 1.18.5 is revised.
Figure 1.18.6 is revised.
Table 1.18.1 is revised.
61
62
63
64
65
66
67
68
72
73
74
75
78
79
81
84
85
86
89
90
91
92
94
95
96
97
98
100
101
102
103
104
105
B1
05/15/01
15
19
31
Figure 1.5.3 is partly revised.
Figure 1.6.2 is partly revised.
Table 1.10.1 is partly revised.
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