參數(shù)資料
型號： M30100M3-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP32
封裝： PLASTIC, LQFP-32
文件頁數(shù)： 100/163頁
文件大?。?/td> 2767K
代理商： M30100M3-XXXFP
Under
development
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
41
Symbol
Address
When reset
INTiIC(i=0, 1, 2)
005D16, 005E16
XX00X0002
005F16
XX00X0002
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2 b1
b0
ILVL0
IR
POL
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
(Note 1)
Interrupt control register
b7
b6
b5
b4
b3
b2 b1
b0
Bit name
Function
Bit symbol
W
R
Symbol
Address
When reset
KUPIC
004D16
XXXXX0002
ADIC
004E16
XXXXX0002
SiTIC(i=0, 1)
005116, 005316
XXXXX0002
SiRIC(i=0, 1)
005216, 005416
XXXXX0002
T1IC
005516
XXXXX0002
TXIC
005616
XXXXX0002
TYIC
005716
XXXXX0002
TZIC
005816
XXXXX0002
CNTR0IC
005916
XXXXX0002
TCINIC
005A16
XXXXX0002
TCIC
005B16
XXXXX0002
INT3IC
005C16
XXXXX0002
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
(Note 1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
Figure 1.12.3. Interrupt control register
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