參數(shù)資料
型號: M2V64S4DTP-7
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁數(shù): 30/51頁
文件大小: 430K
代理商: M2V64S4DTP-7
Feb.'00
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.3.2)
64M Synchronous DRAM
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
30
DQM CONTROL
DQM(U, L) is a dual functional signal defined as the data mask for writes and the output disable for
reads. During writes, DQM(U, L) masks input data word by word. DQM(U, L) to Data In latency is
0. During reads, DQM(U, L) forces output to Hi-Z word by word. DQM(U, L) to output Hi-Z
latency is 2.
DQM Function
CLK
Command
DQ
DQM(U, L)
masked by DQM(U, L)=H
disabled by DQM(U, L)=H
Write
Read
D0
D2
D3
Q0
Q1
Q3
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