參數(shù)資料
型號(hào)： M2V64S4DTP-7
廠商： Mitsubishi Electric Corporation
英文描述： 64M Synchronous DRAM
中文描述： 6400同步DRAM
文件頁(yè)數(shù)： 23/51頁(yè)
文件大?。?/td> 430K
代理商： M2V64S4DTP-7
Feb.'00
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.3.2)
64M Synchronous DRAM
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
23
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQ
Write
Yb
0
00
Dc0
Dc1
Dc2
Dc3
Write
Ya
0
00
Da0
Da1
Da2
Db0
Write
Yc
0
10
CLK
Command
A0-9,11
A10
BA0-1
DQ
ACT
Xa
Xa
00
READ
Yb
0
00
Da0
Da1
Qb0
Write
Ya
0
00
Qb1
Qb2
Qb3
don't care
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