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參數(shù)資料
| 型號(hào)： | M1K-L67142L-70/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 70 ns, CDIP48 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-48 |
| 文件頁(yè)數(shù)： | 14/14頁(yè) |
| 文件大小： | 178K |
| 代理商： | M1K-L67142L-70/883 |
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L67132/L67142
Rev. D (19 Fev. 97)
9
MATRA MHS
Timing Waveform of Write Cycle no 1, R/W Controlled Timing (32, 33, 34, 38)
Timing Waveform of Write Cycle no 2, CS Controlled Timing (32, 33, 34, 36)
Notes :
32. R/W must be high during all address transitions.
33. A write occurs during the overlap (tSW or tWP) of a low CS and a low R/W.
34. tWR is measured from the earlier of CS or R/W going high to the end of write cycle.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high
impedance state.
37. Transition is measured
± 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled
and not 100 % tested.
38. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW)
to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
39. To access RAM, CS = VIL.
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