參數(shù)資料
型號(hào)： M1K-L67142L-70/883
廠商： ATMEL CORP
元件分類： SRAM
英文描述： 2K X 8 DUAL-PORT SRAM, 70 ns, CDIP48
封裝： 0.600 INCH, CERAMIC, DIP-48
文件頁數(shù)： 13/14頁
文件大?。?/td> 178K
代理商： M1K-L67142L-70/883
L67132/L67142
Rev. D (19 Fev. 97)
8
MATRA MHS
AC Parameters
WRITE CYCLE
PARAMETER
L67132–45
L67142–45
L67132–55
L67142–55
L67132–70
L67142–70
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
SYMBOL
(30)
SYMBOL
(31)
PRELIMINARY
TAVAVW
tWC
Write cycle time
45
–
55
–
70
–
ns
TELWH
tSW
Chip select to end of write (28)
35
–
40
–
45
–
ns
TAVWH
tAW
Address valid to end of write
35
–
40
–
45
–
ns
TAVWL
tAS
Address Set–up Time
0
–
0
–
0
–
ns
TWLWH
tWP
Write Pulse Width
35
–
40
–
45
–
ns
TWHAX
tWR
Write Recovery Time
0
–
0
–
0
–
ns
TDVWH
tDW
Data Valid to end of write
25
–
25
–
30
–
ns
TGHQZ
tHZ
Output high Z time (26, 27)
–
20
–
30
–
40
ns
TWHDX
tDH
Data hold time (29)
0
–
0
–
0
–
ns
TWLQZ
tWZ
Write enable to output in high Z (26, 27)
–
20
–
30
–
40
ns
TWHQX
tOW
Output active from end of write (26, 27, 29)
0
–
0
–
0
–
ns
Notes :
26. Transition is measured
± 500 mV from low or high impedance voltage with load (figures 1 and 2).
27. This parameter is guaranteed but not tested.
28. To access RAM CS = VIL.
This condition must be valid for entire tSW time.
29. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions.
Although tDH and tOW values vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
30. STD symbol.
31. ALT symbol.
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