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參數(shù)資料
| 型號(hào)： | M14100-PQG208C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 10000 GATES, 125 MHz, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 105K |
| 代理商： | M14100-PQG208C |
1-407
Actel Mask Programmed Gate Arrays
MPGA Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Preliminary Information
Logic Module Propagation Delays
Parameter
Description
Min.
Max.
Units
tPD
Internal Array Module
1.5
ns
tCO
Sequential Clock to Q
1.5
ns
tCLR
Asynchronous Clear to Q
1.5
ns
Predicted Routing Delays1
tRD1
FO=1 Routing Delay
0.2
ns
tRD2
FO=2 Routing Delay
0.3
ns
tRD3
FO=3 Routing Delay
0.5
ns
tRD4
FO=4 Routing Delay
0.7
ns
tRD8
FO=8 Routing Delay
1.4
ns
Logic Module Sequential Timing
tSUD
Flip-Flop Data Input Setup
1.5
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tSUD
Latch Data Input Setup
1.5
ns
tHD
Latch Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
2.0
ns
tWCLKA
Flip-Flop Clock Pulse Width
2.0
ns
tA
Flip-Flop Clock Input Period
8.0
ns
fMAX
Flip-Flop Clock Frequency
125
MHz
I/O Module Input Propagation Delay
tINY
Input Data Pad to Y
2.0
ns
Predicted Input Routing Delays1
tIRD1
FO=1 Routing Delay
0.2
ns
tIRD2
FO=2 Routing Delay
0.3
ns
tIRD3
FO=3 Routing Delay
0.5
ns
tIRD4
FO=4 Routing Delay
0.7
ns
tIRD8
FO=8 Routing Delay
1.4
ns
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based
on actual routing delay measurements performed on the device prior to shipment.
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