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參數(shù)資料
| 型號： | M-986-2R2PL |
| 廠商： | CLARE INC |
| 元件分類： | 信令電路 |
| 英文描述： | MFC Transceivers |
| 中文描述： | TELECOM, MF SIGNALING CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 520K |
| 代理商： | M-986-2R2PL |
www.clare.com
4
M-986-2R2
Rev. 3
The R2B transceiver detects the signal, enters STATE
2, and outputs the received tone code to its host via the
coprocessor port. If the R2B host had determined the
next tone to transmit and written a transmit command
to the transceiver prior to entry into STATE 2, the state
transition will cause this tone to be transmitted.
Otherwise, the R2B transmitter waits for a transmit
tone command from the host, and starts transmitting a
tone once the transmit tone command is received.
The R2F transceiver detects the backward signal,
enters STATE 2, and outputs the received tone code to
its host. Entry into STATE 2 unconditionally disables
the transmitter.
The R2B transceiver detects the absence of signal,
enters STATE 1, and informs the host with the end-of-
tone code if configured to do so. Entry into STATE 1
unconditionally disables the transmitter.
The R2F transceiver detects the absence of signal,
enters STATE 1, and informs the host with the end-of-
tone code if configured to do so. If the R2F host had
determined the next signal to transmit and written a
transmit command to the transceiver prior to entry into
STATE 1, the state transition will cause this signal to be
transmitted. Otherwise, the transmitter remains silent
until the next transmit command by its host.
Forward/Backward Frequencies (FB): When forward
mode is selected, the R2F (forward) frequencies are
transmitted and R2B (backward) frequencies are
received. When backward mode is selected, R2B fre-
quencies are transmitted and R2F frequencies are
received. The R2F frequencies are 1380, 1500, 1620,
1740, 1860, and 1980 Hertz. The R2B frequencies are
540, 660, 780, 900, 1020, and 1140 Hz.
Initial Configuration: The configuration of the M-986
immediately after a reset will be as follows:
End-of-digit indication ON
Forward mode ON
Channel disabled
2-of-6 input/output
External serial and serial frame clocks.
Also, the M-986 will place 00 hex on the coprocessor
port to indicate to the host processor that it is working.
Transmit Tone Command
The transmit tone command allows the host processor
to transmit any two of the 6 possible frequencies in the
transmission mode the channel has been configured
for (forward or backward). The format of the command
depends on whether the M-986 is configured for bina-
ry format or 2-of-6 format.
Recieved Tone Detection
When a tone is detected by the M-986, the TBLF out-
put goes low, indicating reception of the tone to the
host processor. The host processor can determine
which tone was detected and which channel the tone
was detected on by reading data from the M-986
coprocessor port. The M-986 will return a single byte
indicating the tone received and the channel that the
tone was received on.The format of the returned byte
depends on whether the M-986 is configured for bina-
ry or 2-of-6 coding.
Coprocessor Port
Commands are written to the M-986 via the coproces-
sor port, and data indicating the received R2 MF tone
is read from the coprocessor port.
Writing to the Coprocessor Port: The following
sequence describes writing a command to the M-986.
(1) The WR signal is driven low by the host processor.
(2) The RBLE (receive buffer latch empty) signal tran-
sitions to a logic high level.
(3) Data is written from LD7-LD0 to the receive buffer
latch (D7-D0) when the WR signal goes high.
(4) The RBLE signal transitions to a logic low level after
the M-986 reads the data. This signals the host
processor that the receive buffer is empty.
Note: The RBLE should be low before writing to the
coprocessor.
Reading
the
Coprocessor
Port:
The
following
sequence describes reading received tone information
from the coprocessor port.
(1) The TBLF (transmit buffer latch full) port pin on the
M-986 goes low indicating the reception of a tone.
(2) The host processor detects the low logic level on
the TBLF pin either by polling a connected port pin or
by an interrupt.
(3) The host processor drives the RD signal low.
(4) The TBLF (transmit buffer latch full) signal transi-
tions to a logic high level.
(5) Data is driven onto LD7-LD0 by the M-986 until the
RD signal is driven high by the host processor.
Clock Characeristics and Timing
Internal Clock Option: The internal oscillator is enabled
by connecting a crystal across X1 and X2/CLKIN. The
crystal must be 20.48 MHz, fundamental mode, and
parallel resonant, with an effective series resistance of
30 ohms, a power dissipation of 1 mW, and bespeci-
fied at a load capacitance of 20 pf.
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