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參數(shù)資料
| 型號： | LV24250LS |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | AUDIO TUNER, QCC24 |
| 封裝： | 3.50 X 3.50 MM, VQLP-24 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大小： | 420K |
| 代理商： | LV24250LS |
LV24250LS
LV24250LS latches ACK at the rising edge.
The sequence to write data D into the register A of LV24250LS is shown below.
Start condition
write the device address (C0h)
write the register address, A
write the target data, D
stop condition
SCL
SDA
DA7
start
write device address
write register address
stop
write data byte
DA6...1
Ack
A7
A6...1
D7
D6...0
Ack
Fig. 4 Register write through I2C
When one or more data has been provided for writing, only the first data is allowed to be written.
Read sequence
start condition
write the device address (C0h)
write the register address, A
repeated start condition (or stop + start in a single master network)
write the device address + 1 (C1h)
read the register contents D, transmit NACK (no more data to be read)
stop condition
SCL
SDA
DA7
start
write device address
rep.
write register address
write device address + 1
stop
start
read data byte with NACK
DA6...1
Ack
A7
A6...0
DA7
DA6...1
D7
D6...0
Ack
Fig. 5 Register read through I2C
Interrupt Pin INT
LV24250LS has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected.
The INT output pin is kept floating while the PWRAD bit is cleared during initialization.
Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by
means of the pull-up or pull-down resistor.
This enables direct INT output connection to non-masking interruption of the host CPU.
No.A1699-8/18
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