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參數(shù)資料
| 型號： | LV24250LS |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | AUDIO TUNER, QCC24 |
| 封裝： | 3.50 X 3.50 MM, VQLP-24 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 420K |
| 代理商： | LV24250LS |
LV24250LS
Format of Bus Transfers
Bus transfers are primarily based on the I2C primitives
Start condition
Repeated start condition
Stop condition
Byte write
Byte read
Start, restart, and stop conditions are specified as shown in Table 1 below.
Start
Repeated start
Stop
SCL
SDA
SCL
SDA
SCL
SDA
Fig. 1 the I2C start, repeated start and stop conditions.
For details, like timing, etc., refer to specifications of I2C.
8-bit write
8-bit data is sent from the master microcomputer to LV24250LS.
Data bit consists of MSB first and LSB last.
Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC.
Do not change data while SCL remains HIGH.
LV24250LS outputs the ACK bit between eighth and ninth falling edges of SCL
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Ack
Fig. 2 Signal pattern of the I2C byte write
Read is of the same form as write, only except that the data direction is opposite.
Eight data bits are sent from LV24250LS to the master while Ack is sent from the master to LV24250LS.
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Ack
Fig. 3 Signal pattern of the I2C byte read
The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24250LS in
synchronization with the falling edge while the master side performs latching at the rising edge.
No.A1699-7/18
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