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參數(shù)資料
| 型號(hào)： | LV2134V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 400 MHz, PDSO24 |
| 封裝： | 0.275 INCH, SSOP-24 |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大小： | 83K |
| 代理商： | LV2134V |
LV2134V
No.7928-8/9
Programmable Divider Divisor Data (TX, RX)
The circuit consists of a fixed divide-by-two circuit, a 5-bit swallow counter, and a 10-bit programmable counter.
A divisor, which is a multiple of 2 with a value in the range 1,984 to 65,534 can be set by sending the swallow
counter and programmable counter data.
The programmable counter must be set separately for TX and RX. The counter is set by the above listed address bits
A0 and A1.
The value of the divisor is determined as follows.
Divisor
N=2
× (32×D+A)
D=D0+D1
×21+D2×22+D3×23+ΛΛ+D9×29
A=A0+A1
×21+A2×22+A3×23+A4×24
Reference divider divisor data
The circuit consists of a fixed divide-by-two circuit and a 11-bit reference divider.
A divisor, which is a multiple of 2 with a value of up of 4096, can be set by sending the reference divider data.
The divisor is set by the above listed address bits A0 and A1. The value of the divisor is determined as follows.
Divisor
N=2
×(D0+D1×21+D2×22+D3×23+----+D10×210)
Data
Address
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
A0
A1
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
1
0
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
0
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
1
T1
T2
CPT1
CPT2
LD1
LD2
SBT
CPR1
CPR2
*
SBR
0
About the control data
Controlling the charge pump output current (CPT1, CPT2, CPR1, CPR2)
The IC employs constant-current output type charge pump circuits. Their output current can be controlled using the
control bits CPT1, CPT2 and CPR1, CPR2.
Optimal design of the PLL circuit can be facilitated by switching the charge pump current in lockup and normal
operation modes.
Control bit
CPT1
CPT2
Charge pump current output
0
±0A
0
1
±100A
1
0
±200A
1
±400A
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