參數(shù)資料
型號: LV2134V
元件分類: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, 400 MHz, PDSO24
封裝: 0.275 INCH, SSOP-24
文件頁數(shù): 7/9頁
文件大小: 83K
代理商: LV2134V
LV2134V
No.7928-7/9
Serial Data Format
Serial Data Timing
t1, t4
≥0.1s
t2
≥1s
t5, t3
≥0.2s
About Serial Data
The serial data for controlling the IC must be supplied through the DL, CL, and CE pins (3 pins).
The data bits are loaded into the shift register on the rising edge of clock pulses sequentially starting at the LSB.
After all data bits are loaded, set the CE pin high.
Setting the CE pin high causes the data to be transferred from the shift register to the latch that is designated by the
address data to control the IC.
The latches are available in four groups as shown below. They are designated by address bits A0 and A1.
Address
A0
A1
Description
1
0
Frequency divisor of the TX programmable divider
0
1
Frequency divisor of the RX programmable divider
1
Frequency divisor of the reference divider
0
Control data
D1
D0
A1
A0
D14
D2
D3
15-bit data
CE
CL
DI
D13
D12
D11
D10
D4
2-bit address
MSB
LSB
CE
CL
DI
t1
t2
t3
t4
t5
LSB
MSB
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