- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367612 > LU3X31T-T64 LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX PDF資料下載
參數(shù)資料
| 型號： | LU3X31T-T64 |
| 英文描述： | LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| 中文描述： | LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州 |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Lucent Technologies Inc.
19
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description
(continued)
The autonegotiation link partner ability register at
address 05h indicates the abilities of the link partner as
indicated by autonegotiation communication. The con-
tents of this register are considered valid when the
autonegotiation complete bit (bit 5, register address
01h) is set.
Reset Operation
The LU3X31T-T64 can be reset either by hardware or
software. A hardware reset is accomplished by applying
a negative pulse, with a duration of at least 1 ms, to the
RSTZ pin of the LU3X31T-T64 during normal operation.
A software reset is activated by setting the RESET bit in
the basic mode control register (bit 15, register 00h).
This bit is self-clearing and, when set, will return a
value of 1 until the software reset operation has com-
pleted.
Both hardware and software reset operations initialize
all registers to their default values. This process
includes re-evaluation of all hardware-configurable
registers.
Logic levels on several I/O pins are detected during
hardware reset period to determine the initial function-
ality of LU3X31T-T64. Some of these pins are used as
outputs after the reset operation.
Care must be taken to ensure that the configuration
setup will not interfere with normal operation. Dedi-
cated configuration pins can be tied to V
CC
or ground
directly. Configuration pins multiplexed with logic-level
output functions should be either weakly pulled up or
weakly pulled down through resisters. Configuration
pins multiplexed with LED outputs should be set up
with one of the following circuits shown in Figure 5.
Note: The 10 k
resistor is only for nondefault configuration.
5-6783(F).r2
Figure 5. Hardware Reset Configurations
PHY Address
During hardware reset, the logic levels of pins 10, 12, 16, 34, and 39 are latched into bits 4 through 0 of manage-
ment register at address 19h, respectively. This 5-bit address is used as the PHY address for serial management
interface communication. Note that initializing the PHY address to zero automatically isolates the MII interface.
Autonegotiation and Speed Configuration
The five pins listed in Table 11 configure the speed capability of LU3X31T-T64. The logic state of these pins, at
powerup or reset, are latched into the advertisement register (register address 04h) for autonegotiation purpose.
These pins are also used for evaluating the default value in the base mode control register (register 00h) according
to Table 11.
V
CC
I/O PIN
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
10 k
10 k
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X31T-T64 | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| LU59002 | Consumer IC |
| LU6612 | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| LU6612-T64-DB | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| LU6612 | Single-FET for 10Base-T/100Base-TX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX 的單快速以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。