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參數(shù)資料
| 型號： | LU3X31T-T64 |
| 英文描述： | LU3X31T-T64 Single-Port 3 10/100 Ethernet Transceiver TX |
| 中文描述： | LU3X31T - T64單端口10/100以太網(wǎng)收發(fā)器3得克薩斯州 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 580K |
| 代理商： | LU3X31T-T64 |
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18
Lucent Technologies Inc.
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description
(continued)
Link Test Function.
A link pulse is used to check the
integrity of the connection with the remote end. If valid
link pulses are not received, the link detector disables
the 10Base-T twisted-pair transmitter, receiver, and col-
lision detection functions.
The link pulse generator produces pulses as defined in
the IEEE 802.3 10Base-T standard. Each link pulse is
nominally 100 ns in duration and is transmitted every
16 ms, in the absence of transmit data.
Automatic Link Polarity Detection.
The LU3X31T-
T64's 10Base-T Transceiver Module incorporates an
automatic link polarity detection circuit. The inverted
polarity is determined when seven consecutive link
pulses of inverted polarity or three consecutive receive
packets are received with inverted end of packet
pulses. If the input polarity is reversed, the error condi-
tion will be automatically corrected and reported in bit
15 of register 1Ch.
The automatic link polarity detection function can be
disabled by setting bit 3 of register 1Ah.
Clock Synthesizer
The LU3X31T-T64 implements a clock synthesizer that
generates all the reference clocks needed from a single
external frequency source. The clock source can be a
quartz crystal or a TTL level signal at 25 MHz ±
50 ppm, as shown in Figure 15.
Autonegotiation
The autonegotiation function provides a mechanism for
exchanging configuration information between two
ends of a link segment and automatically selecting the
highest-performance mode of operation supported by
both devices. Fast link pulse (FLP) bursts provide the
signaling used to communicate autonegotiation abilities
between two devices at each end of a link segment. For
further detail regarding autonegotiation, refer to Clause
28 of the IEEE 802.3u specification. The LU3X31T-T64
supports four different Ethernet protocols, so the inclu-
sion of autonegotiation ensures that the highest-perfor-
mance protocol will be selected based on the ability of
the link partner.
The autonegotiation function within the LU3X31T-T64
can be controlled either by internal register access or
by the use of configuration pins. At powerup and at
device reset, the configuration pins are sampled. If dis-
abled, autonegotiation will not occur until software
enables bit 12 in register 0. If autonegotiation is
enabled, the negotiation process will commence imme-
diately.
When autonegotiation is enabled, the LU3X31T-T64
transmits the abilities programmed into the autonegoti-
ation advertisement register at address 04h via FLP
bursts. Any combination of 10 Mbits/s, 100 Mbits/s,
half-duplex, and full-duplex modes may be selected.
Autonegotiation controls the exchange of configuration
information. Upon successful autonegotiation, the abili-
ties reported by the link partner are stored in the auto-
negotiation link partner ability register at address 05h.
The contents of the autonegotiation link partner ability
register are used to automatically configure to the
highest-performance protocol between the local and
far-end nodes. Software can determine which mode
has been configured by autonegotiation by comparing
the contents of register 04h and 05h and then selecting
the technology whose bit is set in both registers of high-
est priority relative to the following list:
1. 100Base-TX full duplex (highest priority)
2. 100Base-TX half duplex
3. 10Base-T full duplex
4. 10Base-T half duplex (lowest priority)
The basic mode control register (BMCR) at address
00h provides control of enabling, disabling, and restart-
ing of the autonegotiation function. When autonegotia-
tion is disabled, the speed selection bit (bit 13) controls
switching between 10 Mbits/s or 100 Mbits/s operation,
while the duplex mode bit (bit 8) controls switching
between full-duplex operation and half-duplex opera-
tion. The speed selection and duplex mode bits have
no effect on the mode of operation when the autonego-
tiation enable bit (bit 12) is set.
The basic mode status register (BSMR) at address 01h
indicates the set of available abilities for technology
types (bits 15 to 11), autonegotiation ability (bit 3), and
extended register capability (bit 0). These bits are hard-
wired to indicate the full functionality of the LU3X31T-
T64. The BMSR also provides status on:
1. Whether autonegotiation is complete (bit 5).
2. Whether the link partner is advertising that a remote
fault has occurred (bit 4).
3. Whether a valid link has been established (bit 2).
The autonegotiation advertisement register at address
04h indicates the autonegotiation abilities to be adver-
tised by the LU3X31T-T64. All available abilities are
transmitted by default, but any ability can be sup-
pressed by writing to this register or configuring exter-
nal pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X31T-T64 | Single-Port 3 V 10/100 Ethernet Transceiver TX/FX(單端口 3 V 10M位和100M位以太網(wǎng)收發(fā)器) |
| LU59002 | Consumer IC |
| LU6612 | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| LU6612-T64-DB | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| LU6612 | Single-FET for 10Base-T/100Base-TX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX 的單快速以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
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