參數(shù)資料
型號(hào)： LTVA
廠(chǎng)商： Linear Technology Corporation
英文描述： 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
中文描述： 1-/2-Channel 20位ADC的無(wú)延遲UPower采用MSOP - 10
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 375K
代理商： LTVA
18
LTC2421/LTC2422
24212f
APPLICATIOU
W
U
U
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 23
μ
s
if the device is using its internal oscillator (F
0
= logic LOW
or HIGH). If F
O
is driven by an external oscillator of fre-
quency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled
HIGH before time t
EOCtest
, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the
24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the con-
version result into external circuitry. EOC can be latched
on the first rising edge of SCK and the last bit of the con-
version result on the
24th
rising edge of SCK. After the
24th
rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and
24th
rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2421/LTC2422’s internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external driver
on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2421/LTC2422’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
Figure 9. Internal Serial Clock, Single Cycle Operation
V
CC
10k
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
ANALOG INPUT RANGE
ZS
SET
– 0.12V
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
μ
F
1
10
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
SDO
SCK
(INTERNAL)
CS
MSB
EXR
SIG
BIT 0
LSB
20
BIT 4
TEST EOC
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
CH0/CH1
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
24212 F09
<t
EOCtest
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TEST EOC
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