參數(shù)資料
型號(hào)： LTVA
廠商： Linear Technology Corporation
英文描述： 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
中文描述： 1-/2-Channel 20位ADC的無延遲UPower采用MSOP - 10
文件頁數(shù)： 17/32頁
文件大小： 375K
代理商： LTVA
17
LTC2421/LTC2422
24212f
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground (Pin 6), simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an inter-
rupt to an external controller indicating the conversion
result is ready. EOC = 1 while the conversion is in progress
and EOC = 0 once the conversion enters the low power
sleep state. On the falling edge of EOC, the conversion
result is loaded into an internal static shift register. The
device remains in the sleep state until the first rising edge
of SCK. Data is shifted out the SDO pin on each falling
edge of SCK enabling external circuitry to latch data on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and con-
trol the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
APPLICATIOU
W
U
U
Figure 8. External Serial Clock, CS = 0 Operation
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
ANALOG INPUT RANGE
ZS
SET
– 0.12V
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
μ
F
1
10
9
2-WIRE SERIAL I/O
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
EOC
CH0/CH1
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSB
EXR
SIG
BIT 0
LSB
20
BIT 4
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
24212 F08
CONVERSION
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