參數(shù)資料
型號: LTM9009IY-14#PBF
廠商: Linear Technology
文件頁數(shù): 25/40頁
文件大?。?/td> 0K
描述: IC ADC 14BIT UMODULE 140-BGA
標準包裝: 210
系列: µModule®
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: Serial LVDS
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 997mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 140-BFBGA
供應(yīng)商設(shè)備封裝: 140-BGA(11.25x9)
包裝: 托盤
輸入數(shù)目和類型: 8 Differential; 8 Single-Ended
31
9009101114fa
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
OUTTEST
X
TP13
TP12
TP11
TP10
TP9
TP8
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bit 5-0
TP13:TP8
Test Pattern Data Bits (MSB)
TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7-0
TP7:TP0
Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
GROUNDING AND BYPASSING
The LTM9011-14/LTM9010-14/LTM9009-14 requires
a printed circuit board with a clean unbroken ground
plane. A multilayer board with an internal ground plane
in the first layer beneath the ADC is recommended.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much
as possible. In particular, care should be taken not to
run any digital track alongside an analog signal track or
underneath the ADC.
Bypass capacitors are integrated inside the package; ad-
ditional capacitance is optional.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
The pin assignments of the LTM9011-14/LTM9010-14/
LTM9009-14 allow a flow-through layout that makes it
possible to use multiple parts in a small area when a large
number of ADC channels are required. The LTM9011
module has similar layout rules to other BGA pack-
ages. The layout can be implemented with 6mil blind
vias and 5mil traces. The pinout has been designed to
minimize the space required to route the analog and
digital traces. The analog and digital traces can essen-
tially be routed within the width of the package. This
allows multiple packages to be located close together
for high channel count applications. Trace lengths for
the analog inputs and digital outputs should be matched
as well as possible.
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