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參數(shù)資料
| 型號： | LTC6603IUF#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER LOWPASS 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 濾波器類型： | 低通 |
| 頻率 - 截止或中心： | 80MHz |
| 濾波器數(shù)： | 2 |
| 濾波器階數(shù)： | 9th |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1323 (CN2011-ZH PDF) |
LTC6603
13
6603fa
APPLICATIONS INFORMATION
Theory of Operation (Refer to Block Diagram)
The LTC6603 features two matched lter channels, each
containing gain control and lowpass lter networks that
are controlled by a single control block and clocked by
a single clock generator. The gain and cutoff frequency
can be separately programmed. The two channels are
not independent, i.e. if the gain is set to 24dB then both
channels have a gain of 24dB. The lter can be clocked
with an external clock source, or using the internal oscil-
lator. A resistor connected to the RBIAS pin sets the bias
currents for the lter networks and the internal oscillator
frequency (unless driven by an external clock). Altering the
clock frequency changes the lter bandwidth. This allows
the lters to be “tuned” to many different bandwidths.
Pin Programmable Interface
As shown in Figure 1, connecting SER to V+D allows the
lter to be directly controlled through the pin program-
mable control lines GAIN1, GAIN0, LPF1 and LPF0. The
GAIN0(D0) pin is bidirectional (input in pin programmable
control mode, output in serial mode). In pin programmable
control mode, the voltage at GAIN0(D0) cannot exceed V+D;
otherwise, large currents can be injected to V+Dthroughthe
parasitic diodes (see Figure 2). Connecting a 10k resistor
at the GAIN0(D0) pin (see Figure 1) is recommended for
current limiting, to less than 10mA. SER has an internal
Figure 1. Filter in Pin Programmable Control Mode
pull-up to V+D. None of the logic inputs have an internal
pull-up or pull-down.
Serial Interface
Connecting SER to ground allows the lter to be controlled
through the SPI serial interface. When CS is low, the serial
data on SDI is shifted into an 8-bit shift register on the
rising edge of the clock (SCLK), with the MSB transferred
rst (see Figure 3). Serial data on SDO is shifted out on
the clock’s falling edge. A high CS will load the 8 bits of
the shift register into an 8-bit D-latch, which is the serial
control register. The clock is disabled internally when
CS is pulled high. Note: SCLK must be low before CS is
pulled low to avoid an extra internal clock pulse. SDO is
always active in serial mode (never tri-stated) and cannot
be “wire-ORed” to other SPI outputs. In addition, SDO is
not forced to zero when CS is pulled high.
An LTC6603 may be daisy-chained with other LTC6603s
or other devices having serial interfaces. Daisy chain-
ing is accomplished by connecting the SDO of the lead
chip to the SDI of the next chip, while SCLK and CS
remain common to all chips in the daisy chain. The se-
rial data is clocked to all the chips then the CS signal
is pulled high to update all of them simultaneously.
Figure 4 shows an example of two LTC6603s in a daisy-
chained SPI conguration.
V+IN
V+A
V+D
+INA
–INA
SER
LPF1(CS)
LPF0(SCLK)
GAIN1
GAIN0(D0)
GND
LTC6603
VOUT
VIN
0.1μF
LOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz)
GAIN = 4
GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.
10k RESISTORS ON GAIN0(OUT) PROTECTS THE
DEVICE WHEN VGAIN0 > V+D
μP
+
–
+
–
+
–
+
–
10k
6603 F01
+OUTA
–OUTA
V+IN
V+A
V+D
+INA
–INA
SER
LPF1(CS)
LPF0(SCLK)
GAIN1
GAIN0(D0)
GND
VOUT
VIN
+OUTA
–OUTA
3.3V
0.1μF
3.3V
LTC6603
LPF1
LPF0
GAIN1
GAIN0
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