參數(shù)資料
型號: LTC4263CDE#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 微控制器/微處理器
英文描述: Single IEEE 802.3af Compliant PSE Controller with Internal Switch; Package: DFN; No of Pins: 14; Temperature Range: 0°C to +70°C
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO14
封裝: 4 X 3 MM, LEAD FREE, PLASTIC, MO-229WGED-3, DFN-14
文件頁數(shù): 19/24頁
文件大小: 349K
代理商: LTC4263CDE#PBF
LTC4263
4
4263fe
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AVACD
Voltage Gain OSC to ACOUT
2V ≤ (VOSC – VSS) ≤ 3V
l
0.95
1.0
1.05
V/V
IACDMAX
AC Disconnect Output Current
VOSC – VSS = 2V, 0V ≤ (VACOUT – VSS) ≤ 4V l
–1
1
mA
IACDMIN
Remain Connected AC Pin Current
VOSC – VSS = 2V
l
130
160
190
μA
VACDEN
AC Disconnect Enable Signal
VOSC – VSS, Port On
l
1.5
V
Digital Interface (Note 10)
VOLED
LED Output Low Voltage
ILED = 10mA
l
1.1
2.2
V
VILD
Digital Input Low Voltage
MIDSPAN, PWRMGT, ENFCLS, SD LEGACY
l
0.8
0.4
V
VIHD
Digital Input High Voltage
MIDSPAN, PWRMGT, ENFCLS, SD LEGACY
l
2.2
V
VOZ
Voltage of Legacy Pin if Left Floating
l
1.1
1.25
1.4
V
IOLEG
Current In/Out of Legacy Pin
0V ≤ (VLEGACY – VSS) ≤ 5V
l
–60
60
μA
IFLT
Maximum Allowed Leakage of External Components
at Legacy Pin in Force Power-On Mode
l
–10
10
μA
Timing Characteristics
tDET
Detection Time
Beginning to End of Detection
l
270
290
310
ms
tDETDLY
Detection Delay
PD Insertion to Detection Complete
l
300
620
ms
tPDC
Classication Duration
l
34
37
39
ms
tPON
Power Turn-On Delay
End of Valid Detect to Application of Power
l
135
145
155
ms
tRISE
Turn-On Rise Time
VDD48 – VOUT: 10% to 90%
CPSE = 0.1μF
l
40
170
μs
tOVLD
Overload/Short-Circuit Time Limit
l
52
62
72
ms
tED
Error Delay
ICUT Fault to Next Detect
l
3.8
4.0
4.2
s
tMPDO
Maintain Power Signature (MPS) Disconnect Delay PD Removal to Power Removal
l
320
350
380
ms
tMPS
MPS Minimum Pulse Width
PD Minimum Current Pulse Width
Required to Stay Connected (Note 11)
l
20
ms
tDBO
Midspan Mode Detection Backoff
RPORT = 15.5kΩ
l
3.0
3.2
3.4
s
tDISDLY
Power Removal Detection Delay
l
0.8
0.95
1.1
s
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are
relative to VSS unless otherwise noted. (Notes 2, 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VSS unless otherwise
specied.
Note 3: 80mA of current may be pulled from the OUT or ACOUT pin
without damage whether the LTC4263 is powered or not. These pins will
also withstand a positive voltage of VSS + 80V.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specied maximum operating junction
temperature may impair device reliability.
Note 5: The LTC4263 operates with a negative supply voltage. To avoid
confusion, voltages in this data sheet are referred to in terms of absolute
magnitude.
Note 6: If the ENFCLS pin is high, ICUT depends on the result of
classication. If ENFCLS pin is low, ICUT reverts to its Class 0 specication.
Note 7: In order to reduce power dissipated in the switch while charging
the PD, the LTC4263 reduces the current limit when VOUT – VSS is large.
Refer to the Typical Performance Characteristics for more information.
Note 8: The LTC4263 includes a high speed current limit circuit intended to
protect against faults. The fault protection is activated for port current
in excess of IFAULT. After the high speed current limit activates, the short-
circuit current limit (ILIM) engages and restricts current to IEEE 802.3af
levels.
Note 9: Class 4 or higher classication current is treated as Class 3.
Note 10: The LTC4263 digital interface operates with respect to VSS. All
logic levels are measured with respect to VSS.
Note 11: The IEEE 802.3af specication allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
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