參數資料
型號： LTC4222IUH#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32
封裝： 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD-X, QFN-32
文件頁數： 28/32頁
文件大?。?/td> 280K
代理商： LTC4222IUH#TRPBF
LTC4222
5
4222fa
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I2C Interface
VADR(H)
ADR0, ADR1, ADR2 Input High Voltage
l
INTVCC
– 0.8
INTVCC
– 0.4
INTVCC
– 0.2
V
IADR(IN,Z)
ADR0, ADR1, ADR2 Hi-Z Input Current
ADR0, ADR1, ADR2 = 0.8V,
INTVCC – 0.8V
l
5
0
–5
μA
VADR(L)
ADR0, ADR1, ADR2 Input Low Voltage
l
0.2
0.4
0.8
V
IADR(IN)
ADR0, ADR1, ADR2 Input Current
ADR0, ADR1, ADR2 = 0V, INTVCC
l
–80
80
μA
VALERT(OL)
ALERT Output Low Voltage
IALERT = 3mA
l
0.2
0.4
V
IALERT(OH)
ALERT Input Current
ALERT = INTVCC
l
±1
μA
VSDA,SCL(TH)
SDA, SCL Input Threshold
l
1.5
1.7
1.9
V
ISDA,SCL(OH)
SDA, SCL Input Current
SCL, SDA = INTVCC
l
±1
μA
VSDA(OL)
SDA Output Low Voltage
ISDA = 3mA
l
0.2
0.4
V
I2C Interface Timing
fSCL(MAX)
SCL Clock Frequency
Operates with fSCL ≤ fSCL(MAX)
400
1000
kHz
tBUF(MIN)
Bus Free Time Between Stop/Start Condition
0.12
1.3
μs
tHD,STA(MIN)
Hold Time After (Repeated) Start Condition
100
600
ns
tSU,STA(MIN)
Repeated Start Condition Set-Up Time
30
600
ns
tSU,STO(MIN)
Stop Condition Set-Up Time
140
600
ns
tHD,DAT(MIN)
Data Hold Time (Input)
30
100
ns
tHD,DATO
Data Hold Time (Output)
300
600
900
ns
tSU,DAT(MIN)
Data Set-Up Time
30
600
ns
tSP
Suppressed Spike Pulse Width
50
110
250
ns
tRST
Stuck-Bus Reset Time
SCL or SDA Held Low
25
32
40
ms
CX
SCL, SDA Input Capacitance
SDAI Tied to SDAO (Note 5)
10
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specied.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: Integral Nonlinearity is dened as the deviation of a code from a
precise analog input voltage. Maximum specications are limited by the
LSB step size and the single shot measurement. Typical specications are
measured from 1/4, 1/2, 3/4 areas of the quantization band.
Note 5: Guaranteed by design and not subject to test.
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