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參數(shù)資料
| 型號： | LTC4215CUFD-2#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-24 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 261K |
| 代理商： | LTC4215CUFD-2#TRPBF |
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LTC4215/LTC4215-2
13
4215fe
APPLICATIONS INFORMATION
dI/dt ramp stops and the inrush current follows the foldback
prole as shown in Figure 2. The TIMER pin integrates at
100μA during start-up and once it reaches its threshold
of 1.235V, the part checks to see if it is in current limit,
which indicates that it has started up into a short-circuit
condition. If this is the case, the overcurrent fault bit, D2
in Table 5, is set and the part turns off. If the part is not in
current limit, the 25mV circuit breaker is armed and the
current limit is switched to 75mV. Alternately an internal
100ms start-up timer may be selected by tying the TIMER
pin to INTVCC.
As the SOURCE voltage rises, the FB pin follows as set
by R7 and R8. Once FB crosses its 1.235V threshold, and
the start-up timer has expired, the GPIO pin, in its default
conguration, ceases to pull low and indicates that power
is now good.
generates an OC fault, or the FB pin voltage crosses its
1.235V power good threshold and the GPIO pin signals
power good.
GATE Pin Voltage
A curve of GATE-to-SOURCE drive vs VDD is shown in the
Typical Performance Characteristics. At minimum input
supply voltage of 2.9V, the minimum GATE-to-SOURCE
drive voltage is 4.7V. The GATE-to-SOURCE voltage is
clamped below 6.5V to protect the gates of logic level
N-channel MOSFETs.
Turn-Off Sequence
The GATE is turned off by a variety of conditions. A normal
turn-off is initiated by the ON pin going low or a serial bus
turn-off command. Additionally, several fault conditions
turn off the GATE. These include an input overvoltage
(OV pin), input undervoltage (UV pin), overcurrent circuit
breaker (SENSE– pin), or EN transitioning high. Writing
a logic one into the UV, OV or OC fault bits (D0-D2 in
Table 5) also latches off the GATE if their auto-retry bits
are set to false.
Normally the MOSFET is turned off with a 1mA current
pulling down the GATE pin to ground. With the MOSFET
turned off, the SOURCE and FB voltages drop as CL dis-
charges. When the FB voltage crosses below its threshold,
GPIO pulls low to indicate that the output power is no
longer good.
If the VDD pin falls below 2.74V for greater than 2μs or
INTVCC drops below 2.60V for greater than 1μs, a fast shut
down of the MOSFET is initiated. The GATE pin is pulled
down with a 450mA current to the SOURCE pin.
Overcurrent Fault
The LTC4215 features an adjustable current limit that
protects against short circuits or excessive load current.
An overcurrent fault occurs when the circuit breaker 25mV
threshold has been exceeded for longer than the 20μs
(LTC4215) or 420μs (LTC4215-2) time-out delay. Current
limiting begins immediately when the current sense voltage
between the VDD and SENSE pins reaches 75mV. The GATE
VDD + 6V
VGATE
VOUT
GPIO1
(POWER GOOD)
ILOAD RSENSE
VDD
VSENSE
25mV
10mV
SS
LIMITED
FB
LIMITED
4215 F02
TIMER
EXPIRES
tSTARTUP
Figure 2. Power-Up Waveforms
If R6 and C1 are employed for a constant current during
start-up, which produces a constant dV/dt at the output,
a 20μA pull-up current from the gate pin slews the gate
upwards and the part is not in current limit. The start-up
TIMER may expire in this condition and an OC fault is not
generated even though start-up has not completed. Either
the sense voltage increases to the 25mV CB threshold and
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| LTC4215IUFD-2 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
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| LTC4215CUFD-3#TRPBF | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| LTC4215CUFD-3 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
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