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參數(shù)資料
| 型號(hào)： | LTC4155IUFD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC28 |
| 封裝： | 5 X 4 MM, 0.75 MM HEIGHT, PLASTIC, MO-220WXXX-X, QFN-28 |
| 文件頁數(shù)： | 21/52頁 |
| 文件大小： | 473K |
| 代理商： | LTC4155IUFD#TRPBF |
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LTC4155
28
4155f
master transmits an ACK or a NACK is irrelevant. Finally,
a STOP condition returns the bus to the idle state.
SMBus Send Byte Protocol
1
7
1 1
8
1 1
S
SLAVE ADDRESS
WR A
DATA BYTE
A P
The SMBus send byte protocol can be used to modify
the contents of the sub address pointer register without
modifying the contents of any control registers. It has util-
ity when preparing to later read status information from
the LTC4155 using the SMBus receive byte protocol. The
transaction is initiated by the bus master with a START
condition. The SMBus slave address corresponds to the
LTC4155writeaddress,whichis0x09wheninterpretedasa
7-bit word (0b 000 1001) followed by WR (value 0b0). The
LTC4155 will acknowledge its write address. The SMBus
data byte corresponds to the sub address pointer value
and will be written to the sub address pointer register in
the LTC4155. Note that the data byte in this protocol is
analogous to the command code in the write byte and
read byte protocols. The LTC4155 will acknowledge the
SMBus data byte. Finally, a STOP condition returns the
bus to the idle state.
SMBus Receive Byte Protocol
1
7
1 1
8
1 1
S
SLAVE ADDRESS
RD A
DATA BYTE
A P
The SMBus receive byte protocol can be used to read
the contents of the command or status register already
selected by the sub address pointer register. This protocol
is incapable of modifying the contents of the sub address
pointer register, but may be useful to poll a single status
register repeatedly with much less bus overhead than the
other SMBus protocols. The sub address pointer register
can be modified by any of the SMBus write byte, read
byte or send byte protocols and the register contents
will persist until they are modified again by one of these
three protocols.
The receive byte transaction is initiated by the bus master
with a START condition. The SMBus slave address corre-
sponds to the LTC4155 read address, which is 0x09 when
interpreted as a 7-bit word (0b 000 1001), followed by
RD (value 0b1). The LTC4155 will acknowledge its read
address. At this time the bus master becomes a receiver
while continuing to clock SCL. The LTC4155 becomes a
slave transmitter and controls SDA to place data on the
bus. Following the single data byte, the bus master has
the option of transmitting either an ACK or a NACK bit.
According to the I2C specification, a master must trans-
mit a NACK at the end of a read transaction to instruct
the slave to terminate data transmission. Because the
LTC4155 terminates data transmission after one byte in
all cases, whether the bus master transmits an ACK or a
NACK is irrelevant. Finally, a STOP condition returns the
bus to the idle state.
Programmable Interrupt Controller
The LTC4155 can optionally generate active LOW, level-
triggered interrupt requests on the IRQ pin in response
to a number of status change or fault events. The three
available bytes of status information are also frozen at
the time the interrupt is triggered to aid in determining
the cause of a transient interrupt. The contents of the
four writeable command registers are never frozen by
interrupts. The interrupt trigger events are grouped into
six individually maskable categories corresponding to
battery charger status, faults, input power detection, USB
On-The-Go,inputcurrentlimitandinputundervoltagecur-
rent limit. The interrupt mask register (IMR) is located at
sub address location 0x06, with the six most significant
bits representing the mask programming. Refer to Table3.
Table 4 lists the status triggers for each interrupt category.
Uponpower-up,allinterruptsdefaulttodisabled(masked).
Each interrupt category may be enabled by writing a “1”
to the appropriate position in the IMR. Any data written to
sub address 0x06 also has the side effect of clearing the
pending interrupt upon the acknowledge bit of the data
(third) byte. Clearing the interrupt releases the IRQ pin
and resumes status reporting of live data until the next
interrupt. If no change to the interrupt mask is desired, the
bus master must rewrite the previous data to sub address
0x06 to clear an interrupt request.
OPERATION
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