參數(shù)資料
型號(hào)： LTC3890IGN-1#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, PDSO28
封裝： LEAD FREE, PLASTIC, SSOP-28
文件頁數(shù)： 11/36頁
文件大?。?/td> 498K
代理商： LTC3890IGN-1#PBF
LTC3890-1
19
38901f
APPLICATIONS INFORMATION
Figure 5. Setting Output Voltage
RMS capacitor current requirement. Increasing the out-
put current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
IMAX
VIN
VOUT
() VIN –VOUT
()
1/ 2
(1)
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even signicant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3890-1, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benet of the LTC3890-1 2-phase operation can be
calculated by using Equation 1 for the higher power control-
ler and then calculating the loss that would have resulted
if both controller channels switched on at the same time.
The total RMS power lost is lower when both controllers
are operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benet of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efciency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the drains and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3890-1, is
also suggested. A 10Ω resistor placed between CIN (C1)
and the VIN pin provides further isolation between the
two channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satised, the capacitance is adequate for ltering. The
output ripple (ΔVOUT) is approximated by:
VOUT
IL ESR+
1
8 f COUT
where f is the operating frequency, COUT is the output
capacitance and ΔIL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage.
Setting Output Voltage
The LTC3890-1 output voltages are each set by an exter-
nal feedback resistor divider carefully placed across the
output, as shown in Figure 5. The regulated output voltage
is determined by:
VOUT = 0.8V 1+
RB
RA
To improve the frequency response, a feedforward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
1/2 LTC3890-1
VFB
VOUT
RB
CFF
RA
38901 F05
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