參數(shù)資料
型號(hào): LTC3835IUFD
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3 A SWITCHING CONTROLLER, 580 kHz SWITCHING FREQ-MAX, PQCC20
封裝: 4 X 5 MM, PLASTIC, MO-220, QFN-20
文件頁(yè)數(shù): 11/30頁(yè)
文件大?。?/td> 1775K
代理商: LTC3835IUFD
LTC3835
19
3835fd
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3835 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the top MOSFET (TG)
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
external filter network connected to the PLLLPF pin. The
relationship between the voltage on the PLLLPF pin and
operating frequency, when there is a clock signal applied
to PLLIN/MODE, is shown in Figure 7 and specified in the
Electrical Characteristics table. Note that the LTC3835 can
onlybesynchronizedtoanexternalclockwhosefrequency
is within range of the LTC3835’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a stable
input to the voltage-controlled oscillator. The filter compo-
nents CLP and RLP determine how fast the loop acquires
lock. Typically RLP = 10k and CLP is 2200pF to 0.01F.
Typically,theexternalclock(onPLLIN/MODEpin)inputhigh
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
PLLIN/MODE
PIN
FREQUENCY
0V
DC Voltage
250kHz
Floating
DC Voltage
400kHz
INTVCC
DC Voltage
530kHz
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
Figure 7. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
PLLLPF PIN VOLTAGE (V)
0
FREQUENCY
(kHz)
0.5
1
1.5
2
3835 F07
2.5
0
100
300
400
500
900
800
700
200
600
Figure 8. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
RLP
CLP
3835 F08
PLLLPF
EXTERNAL
OSCILLATOR
PLLIN/
MODE
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