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參數(shù)資料
| 型號： | LTC2627CDE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Dual Rail-to-Rail with I2C Interface; Package: DFN; No of Pins: 12; Temperature Range: 0°C to +70°C |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PDSO12 |
| 封裝： | 4 X 3 MM, EXPOSED PAD, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 333K |
| 代理商： | LTC2627CDE#TR |
10
LTC2607/LTC2617/LTC2627
26071727f
PIN FUNCTIONS
UU
U
CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
CA1 (Pin 2): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
LDAC (Pin 3): Asynchronous DAC Update. A falling edge
of this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part wakes up sleeping DACs without
updating the DAC output. Software power-down is dis-
abled when LDAC is low. LDAC is disabled when tied high.
SCL (Pin 4): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current source
to VCC.
SDA (Pin 5): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in and an open-
drain N-channel output during acknowledgment. Requires
a pull-up resistor or current source to VCC.
CA2 (Pin 6): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (Table 1).
VOUTB (Pin 7): DAC Analog Voltage Output. The output
range is VREFLO to VREF.
VCC (Pin 8): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
REF (Pin 9): Reference Voltage Input. The input range
is VREFLO ≤ VREF ≤ VCC.
GND (Pin 10): Analog Ground.
REFLO (Pin 11): Reference Low. The voltage at this pin
sets the zero scale (ZS) voltage of all DACs. The VREFLO pin
can be used at voltages up to 1V for VCC = 5V, or 100mV
for VCC = 3V.
VOUTA (Pin 12): DAC Analog Voltage Output. The output
range is VREFLO to VREF.
Exposed Pad (Pin 13): Ground. Must be soldered to
PCB ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2627CDE-1#TR | 12-Bit Dual Rail-to-Rail with I2C Interface; Package: DFN; No of Pins: 12; Temperature Range: 0°C to +70°C |
| LTC2627IDE#TR | 12-Bit Dual Rail-to-Rail with I2C Interface; Package: DFN; No of Pins: 12; Temperature Range: -40°C to +85°C |
| LTC2627IDE-1#TR | 12-Bit Dual Rail-to-Rail with I2C Interface; Package: DFN; No of Pins: 12; Temperature Range: -40°C to +85°C |
| LTC2629CGN#TR | Quad 12-Bit Rail-to-Rail DACs with I2C Interface; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C |
| LTC2629CGN-1#TR | Quad 12-Bit Rail-to-Rail DACs with I2C Interface; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C |
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參數(shù)描述 |
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