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參數(shù)資料
| 型號： | LTC2626IDD#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Rail-to-Rail DACs with I2C Interface; Package: DFN; No of Pins: 10; Temperature Range: -40°C to +85°C |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封裝： | 3 X 3 MM, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 273K |
| 代理商： | LTC2626IDD#TR |
LTC2606/LTC2616/LTC2626
4
26061626fb
ELECTRICAL CHARACTERISTICS The ● denotes specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted. (Note 11)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PSR
Power Supply Rejection
VCC = ±10%
–81
dB
ROUT
DC Output Impedance
VREF = VCC = 5V, Mid-Scale; –15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.7V, Mid-Scale; –7.5mA ≤ IOUT ≤
●
0.05
0.06
0.15
Ω
ISC
Short-Circuit Output Current
VCC = 5.5V, VREF = 5.5V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
●
15
34
36
60
mA
VCC = 2.7V, VREF = 2.7V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
●
7.5
22
29
50
mA
Reference Input
Input Voltage Range
●
0VCC
V
Resistance
Normal Mode
●
88
124
160
kΩ
Capacitance
15
pF
IREF
Reference Current, Power Down Mode
DAC Powered Down
●
0.001
1
μA
Power Supply
VCC
Positive Supply Voltage
For Specied Performance
●
2.7
5.5
V
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
●
0.340
0.27
0.35
0.10
0.5
0.4
1
mA
μA
Digital I/O (Note 11)
VIL
Low Level Input Voltage (SDA and SCL)
●
–0.5
0.3VCC
V
VIH
High Level Input Voltage (SDA and SCL)
(Note 8)
●
0.7VCC
V
VIL(LDAC) Low Level Input Voltage (LDAC)VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
●
0.8
0.6
V
VIH(LDAC) High Level Input Voltage (LDAC)VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
●
2.4
2.0
V
VIL(CAn)
Low Level Input Voltage on CA
n
(
n = 0, 1, 2)
See Test Circuit 1
●
0.15VCC
V
VIH(CAn)
High Level Input Voltage on CA
n
(
n = 0, 1, 2)
See Test Circuit 1
●
0.85VCC
V
RINH
Resistance from CA
n (n = 0, 1, 2)
to VCC to Set CAn = VCC
See Test Circuit 2
●
10
kΩ
RINL
Resistance from CA
n (n = 0, 1, 2)
to GND to Set CA
n = GND
See Test Circuit 2
●
10
kΩ
RINF
Resistance from CA
n (n = 0, 1, 2)
to VCC or GND to Set CAn = Float
See Test Circuit 2
●
2MΩ
VOL
Low Level Output Voltage
Sink Current = 3mA
●
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 9)
●
20 + 0.1CB
250
ns
tSP
Pulse Width of Spikes Suppressed
by Input Filter
●
050
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
●
1μA
CIN
I/O Pin Capacitance
(Note 4)
●
10
pF
CB
Capacitive Load for Each Bus Line
●
400
pF
CCAX
External Capacitive Load on Address
Pins CA
n (n = 0, 1, 2)
●
10
pF
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