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參數(shù)資料
| 型號： | LTC2453IDDBTRMPBF |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Easy-to-Use, Ultra-Tiny, Differential, 16-Bit ADC With I2C Interface |
| 中文描述： | 易于使用，超微型，差分，16位ADC，帶有I2C接口 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 223K |
| 代理商： | LTC2453IDDBTRMPBF |
LTC2453
9
2453f
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NAK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a Read
Request. If the 7-bit address matches the LTC2453’s ad-
dress (hard-wired at 0010100) the ADC is selected. When
the device is addressed during the conversion state, it does
not accept the request and issues a NAK by leaving the
SDA line HIGH. If the conversion is complete, the LTC2453
issues an ACK by pulling the SDA line LOW.
Following the ACK, the LTC2453 can output data. The data
output stream is 16 bits long and is shifted out on the
falling edges of SCL (see Figure 4). The first bit output by
the LTC2453 is the sign, which is 1 for V
IN+
≥ V
IN–
and 0
for V
IN+
< V
IN–
. The next bit is the MSB (D14) and is fol-
lowed by successively less significant bits (D13, D12…)
until the LSB is output by the LTC2453. This sequence is
shown in Figure 5.
OPERATION SEQUENCE
Continuous Read
Conversions from the LTC2453 can be continuously
read, see Figure 6. At the end of a read operation, a new
conversion automatically begins. At the conclusion of
the conversion cycle, the next result may be read using
the method described above. If the conversion cycle is
not complete and a valid address selects the device, the
LTC2453 generates a NAK signal indicating the conversion
cycle is in progress.
SDA
SCL
S
Sr
P
S
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
2453 F03
Figure 3. Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
1
7
8
9
2
3
1
8
D8
D13
D14
SGN
MSB
D15
R
SDA
SCL
7-BIT
ADDRESS
START BY
MASTER
D7
D6
D5
D0
LSB
9
1
2
3
8
9
ACK BY
LTC2453
ACK BY
MASTER
NACK BY
MASTER
SLEEP
DATA OUTPUT
CONVERSION
2453 F04
Figure 4. Read Sequence Timing Diagram
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