參數(shù)資料
型號(hào)： LTC2453IDDBTRMPBF
廠商： Linear Technology Corporation
英文描述： Easy-to-Use, Ultra-Tiny, Differential, 16-Bit ADC With I2C Interface
中文描述： 易于使用，超微型，差分，16位ADC，帶有I2C接口
文件頁(yè)數(shù)： 8/16頁(yè)
文件大?。?/td> 223K
代理商： LTC2453IDDBTRMPBF
LTC2453
8
2453f
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF
+
and REF
–
pins covers the entire operating range of
the device (GND to V
CC
). For correct converter operation,
V
REF+
must be >(2.5V + V
REF–
).
The LTC2453 differential reference input range is 2.5V to
V
CC
. For the simplest operation, REF
+
can be shorted to
V
CC
and REF
–
can be shorted to GND.
Input Voltage Range
For most applications, V
REF–
≤ (V
IN+
, V
IN–
) ≤ V
REF+
. Under
these conditions the output code is given (see Data Format
section) as 32768 (V
IN+
– V
IN–
)/(V
REF+
– V
REF–
). The
output of the LTC2453 is clamped at a maximum value of
32767 and clamped at a minimum value of –32768.
The LTC2453 includes a proprietary system that can,
typically, correctly digitize each input 8LSB above V
REF+
and below V
REF–
, if the LTC2453’s output is not clamped.
As an example (Figure 2), if the user desires to measure
a signal slightly below ground, the user could set V
IN–
=
V
REF–
= GND, and V
REF+
= 5V. If V
IN+
= GND, the output
code would be approximately 0. If V
IN+
= GND – 8LSB =
–1.22 mV, the output code would be approximately –8.
I
2
C INTERFACE
The LTC2453 communicates through an I
2
C interface. The
I
2
C interface is a 2-wire open-drain interface supporting
multiple devices and masters on a single bus. The con-
nected devices can only pull the data line (SDA) LOW and
never drive it HIGH. SDA must be externally connected to
the supply through a pull-up resistor. When the data line
is free, it is HIGH. Data on the I
2
C bus can be transferred
at rates up to 100kbits/s in the Standard-Mode and up to
400kbits/s in the Fast-Mode.
Each device on the I
2
C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2453 is 0010100.
The LTC2453 can only be addressed as a slave. It can only
transmit the last conversion result. The serial clock line,
SCL, is always an input to the LTC2453 and the serial data
line SDA is bidirectional. Figure 3 shows the definition of
the I
2
C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
V
IN+
/V
REF+
–0.001
O
4
12
20
0.001
2453 F02
–4
–12
0
8
16
–8
–16
–20
–0.005
0
0.005
0.0015
SIGNALS
BELOW
GND
Figure 2. Output Code vs V
IN+
with V
IN–
= 0 and V
REF–
= 0
APPLICATIONS INFORMATION
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